| Message ID | 1521599960-34381-2-git-send-email-shawn.lin@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Am Mittwoch, 21. März 2018, 03:39:19 CET schrieb Shawn Lin: > commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase > if clock rate is zero") catches one gremlin again for clk-rk3228.c > that the parent of SDMMC phase clock should be sclk_sdmmc0, but not > sclk_sdmmc. However, I don't like the name of sclk_sdmmc0, so I now > rename it to be sclk_sdmmc. > > Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> applied to my clk-branch after adapting the commit message a bit, so that it is less about personal taste and highlights the discrepancy in the manual between clk_sdmmc0 and hclk_sdmmc (without 0) and we thus standardize on the one without 0. Heiko
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c index 11e7f2d..7af4818 100644 --- a/drivers/clk/rockchip/clk-rk3228.c +++ b/drivers/clk/rockchip/clk-rk3228.c @@ -387,7 +387,7 @@ enum rk3228_plls { RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS, RK2928_CLKGATE_CON(2), 15, GFLAGS), - COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, + COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0, RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS, RK2928_CLKGATE_CON(2), 11, GFLAGS),
commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase if clock rate is zero") catches one gremlin again for clk-rk3228.c that the parent of SDMMC phase clock should be sclk_sdmmc0, but not sclk_sdmmc. However, I don't like the name of sclk_sdmmc0, so I now rename it to be sclk_sdmmc. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> --- drivers/clk/rockchip/clk-rk3228.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)