From patchwork Fri Jun 5 15:52:48 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 6556241 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 975F99F1C1 for ; Fri, 5 Jun 2015 15:53:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A43D5206E0 for ; Fri, 5 Jun 2015 15:53:32 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BC959206D9 for ; Fri, 5 Jun 2015 15:53:30 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z0tw2-0002br-BL; Fri, 05 Jun 2015 15:53:30 +0000 Received: from gloria.sntech.de ([95.129.55.99]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z0tvz-0002U7-Eh; Fri, 05 Jun 2015 15:53:29 +0000 Received: from ip92344111.dynamic.kabel-deutschland.de ([146.52.65.17] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1Z0tvN-0002j7-0K; Fri, 05 Jun 2015 17:52:49 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Caesar Wang Subject: Re: [PATCH v3 1/3] ARM: rockchip: fix the CPU soft reset Date: Fri, 05 Jun 2015 17:52:48 +0200 Message-ID: <1744325.yNd0r8SV4R@diego> User-Agent: KMail/4.14.1 (Linux/3.16.0-4-amd64; KDE/4.14.2; x86_64; ; ) In-Reply-To: <1433517104-7595-2-git-send-email-wxt@rock-chips.com> References: <1433517104-7595-1-git-send-email-wxt@rock-chips.com> <1433517104-7595-2-git-send-email-wxt@rock-chips.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150605_085327_701088_C1005D13 X-CRM114-Status: GOOD ( 14.80 ) X-Spam-Score: -0.0 (/) Cc: Russell King , Dmitry Torokhov , dianders@chromium.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi Caesar, Am Freitag, 5. Juni 2015, 23:11:42 schrieb Caesar Wang: > We need different orderings when turning a core on and turning a core > off. In one case we need to assert reset before turning power off. > In ther other case we need to turn power on and the deassert reset. > > In general, the correct flow is: > > CPU off: > reset_control_assert > regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), BIT(pd)) > CPU on: > regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), 0) > reset_control_deassert > > This is needed for stressing CPU up/down, as per: > cd /sys/devices/system/cpu/ > for i in $(seq 1000); do > echo "================= $i ============" > for j in $(seq 100); do > while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat > cpu3/online)" != "000"" ]] echo 0 > cpu1/online > echo 0 > cpu2/online > echo 0 > cpu3/online > done > while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat > cpu3/online)" != "111" ]]; do echo 1 > cpu1/online > echo 1 > cpu2/online > echo 1 > cpu3/online > done > done > done > > The following is reproducile log: > [34466.186812] PM: noirq suspend of devices complete after 0.669 msecs > [34466.186824] Disabling non-boot CPUs ... > [34466.187509] CPU1: shutdown > [34466.188672] CPU2: shutdown > [34473.736627] Kernel panic - not syncing:Watchdog detected hard LOCKUP > on cpu 0 ....... > > Signed-off-by: Caesar Wang > --- could we do this something like the shown below instead? Here the deassertion of the reset really happens after we are sure the power-domain is on -------------- 8< --------------- -------------- 8< --------------- diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index 5b4ca3c..ee5dbad6 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -72,6 +72,7 @@ static struct reset_control *rockchip_get_core_reset(int cpu) static int pmu_set_power_domain(int pd, bool on) { u32 val = (on) ? 0 : BIT(pd); + struct reset_control *rstc = rockchip_get_core_reset(pd); int ret; /* @@ -80,20 +81,16 @@ static int pmu_set_power_domain(int pd, bool on) * processor is powered down. */ if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) { - struct reset_control *rstc = rockchip_get_core_reset(pd); - + /* We only require the reset on the RK3288 at the moment */ if (IS_ERR(rstc)) { pr_err("%s: could not get reset control for core %d\n", __func__, pd); return PTR_ERR(rstc); } - if (on) - reset_control_deassert(rstc); - else + if (!on) reset_control_assert(rstc); - reset_control_put(rstc); } ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val); @@ -112,6 +109,12 @@ static int pmu_set_power_domain(int pd, bool on) } } + if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9 && on) + reset_control_deassert(rstc); + + if (!IS_ERR(rstc)) + reset_control_put(rstc); + return 0; }