From patchwork Fri Sep 2 15:55:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 9311279 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8362560756 for ; Fri, 2 Sep 2016 15:55:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 73A382977A for ; Fri, 2 Sep 2016 15:55:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 67FC5297D1; Fri, 2 Sep 2016 15:55:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E25982977A for ; Fri, 2 Sep 2016 15:55:25 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bfqoP-0007Dl-Id; Fri, 02 Sep 2016 15:55:25 +0000 Received: from mail.kernel.org ([198.145.29.136]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bfqoM-0006Gp-LS for linux-rockchip@lists.infradead.org; Fri, 02 Sep 2016 15:55:23 +0000 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A137420397; Fri, 2 Sep 2016 15:55:04 +0000 (UTC) Received: from localhost (173-27-161-33.client.mchsi.com [173.27.161.33]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6298220394; Fri, 2 Sep 2016 15:55:03 +0000 (UTC) Subject: [PATCH v2 08/15] Remove duplicate CSR definition. To: Shawn Lin From: Bjorn Helgaas Date: Fri, 02 Sep 2016 10:55:01 -0500 Message-ID: <20160902155501.8650.92863.stgit@bhelgaas-glaptop2.roam.corp.google.com> In-Reply-To: <20160902154501.8650.99790.stgit@bhelgaas-glaptop2.roam.corp.google.com> References: <20160902154501.8650.99790.stgit@bhelgaas-glaptop2.roam.corp.google.com> User-Agent: StGit/0.16 MIME-Version: 1.0 X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160902_085522_823121_84E83782 X-CRM114-Status: GOOD ( 12.01 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Brian Norris , Heiko Stuebner , Arnd Bergmann , Marc Zyngier , linux-pci@vger.kernel.org, Wenrui Li , linux-kernel@vger.kernel.org, Doug Anderson , linux-rockchip@lists.infradead.org, Rob Herring , Guenter Roeck Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP PCIE_RC_CONFIG_LCSR was the same as PCIE_RC_CONFIG_LCS. Kept PCIE_RC_CONFIG_LCS. PCIE_CORE_LCSR_RETRAIN_LINK was inexplicably named differently and defined separately. --- drivers/pci/host/pcie-rockchip.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index b204567..a2dd196 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -40,11 +40,12 @@ #define PCIE_CLIENT_BASE 0x0 #define PCIE_RC_CONFIG_BASE 0xa00000 #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 0x90c -#define PCIE_RC_CONFIG_LCSR 0xd0 -#define PCIE_RC_CONFIG_LCSR_LBMIE BIT(10) -#define PCIE_RC_CONFIG_LCSR_LABIE BIT(11) -#define PCIE_RC_CONFIG_LCSR_LBMS BIT(30) -#define PCIE_RC_CONFIG_LCSR_LAMS BIT(31) +#define PCIE_RC_CONFIG_LCS 0xd0 +#define PCIE_RC_CONFIG_LCS_RETRAIN_LINK BIT(5) +#define PCIE_RC_CONFIG_LCS_LBMIE BIT(10) +#define PCIE_RC_CONFIG_LCS_LABIE BIT(11) +#define PCIE_RC_CONFIG_LCS_LBMS BIT(30) +#define PCIE_RC_CONFIG_LCS_LAMS BIT(31) #define PCIE_CORE_CTRL_MGMT_BASE 0x900000 #define PCIE_CORE_AXI_CONF_BASE 0xc00000 #define PCIE_CORE_AXI_INBOUND_BASE 0xc00800 @@ -68,7 +69,6 @@ #define PCIE_CLIENT_INT_HOT_PLUG BIT(1) #define PCIE_CLIENT_INT_PWR_STCG BIT(0) #define PCIE_RC_CONFIG_RID_CCR 0x8 -#define PCIE_RC_CONFIG_LCS 0xd0 #define PCIE_RC_BAR_CONF 0x300 #define PCIE_CORE_OB_REGION_ADDR1 0x4 #define PCIE_CORE_OB_REGION_DESC0 0x8 @@ -119,7 +119,6 @@ #define RC_REGION_0_ADDR_TRANS_L 0x00000000 #define RC_REGION_0_PASS_BITS (25 - 1) #define MAX_AXI_WRAPPER_REGION_NUM 33 -#define PCIE_CORE_LCSR_RETRAIN_LINK BIT(5) /* * The upper 16 bits of the PCIE_CLIENT registers are a write mask for the @@ -204,18 +203,18 @@ static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip) { u32 status; - status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR); - status |= (PCIE_RC_CONFIG_LCSR_LBMIE | PCIE_RC_CONFIG_LCSR_LABIE); - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR); + status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCS); + status |= (PCIE_RC_CONFIG_LCS_LBMIE | PCIE_RC_CONFIG_LCS_LABIE); + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCS); } static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip) { u32 status; - status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR); - status |= (PCIE_RC_CONFIG_LCSR_LBMS | PCIE_RC_CONFIG_LCSR_LAMS); - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR); + status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCS); + status |= (PCIE_RC_CONFIG_LCS_LBMS | PCIE_RC_CONFIG_LCS_LAMS); + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCS); } static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip, @@ -506,7 +505,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) */ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS + PCIE_RC_CONFIG_BASE); - status |= PCIE_CORE_LCSR_RETRAIN_LINK; + status |= PCIE_RC_CONFIG_LCS_RETRAIN_LINK; rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS + PCIE_RC_CONFIG_BASE);