| Message ID | 20161104131056.GA9801@vaio-ubuntu (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Am Freitag, 4. November 2016, 14:10:56 CET schrieb Paweł Jarosz: > We need this to init PLL_CPLL to 400MHz at boot. > > Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> applied to my clk branch for 4.10 Thanks Heiko
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index a6d398f..062ef49 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -89,6 +89,7 @@ static struct rockchip_pll_rate_table rk3188_pll_rates[] = { RK3066_PLL_RATE( 504000000, 1, 84, 4), RK3066_PLL_RATE( 456000000, 1, 76, 4), RK3066_PLL_RATE( 408000000, 1, 68, 4), + RK3066_PLL_RATE( 400000000, 3, 100, 2), RK3066_PLL_RATE( 384000000, 2, 128, 4), RK3066_PLL_RATE( 360000000, 1, 60, 4), RK3066_PLL_RATE( 312000000, 1, 52, 4),
We need this to init PLL_CPLL to 400MHz at boot. Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> --- drivers/clk/rockchip/clk-rk3188.c | 1 + 1 file changed, 1 insertion(+)