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[80.198.72.241]) by smtp.gmail.com with ESMTPSA id d27sm1658339lfb.73.2018.02.26.10.57.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 26 Feb 2018 10:57:37 -0800 (PST) From: Vicente Bergas To: =?UTF-8?q?Heiko=20St=C3=BCbner?= , linux-rockchip@lists.infradead.org Subject: [PATCH] arm64: dts: rockchip: move rk3399-sapphire PCIe to excavator baseboard Date: Mon, 26 Feb 2018 19:57:21 +0100 Message-Id: <20180226185721.2582-1-vicencb@gmail.com> X-Mailer: git-send-email 2.16.2 In-Reply-To: <3840224.sEPfbROKII@phil> References: <3840224.sEPfbROKII@phil> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180226_105751_059923_B8CB8EAE X-CRM114-Status: UNSURE ( 9.58 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vicente Bergas MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The PCIe signals are routed through the connector to the baseboard. Signed-off-by: Vicente Bergas Tested-by: Vicente Bergas Reviewed-by: Shawn Lin --- .../arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts | 15 +++++++++++++++ arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi | 15 --------------- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts index 56952d1a3fb8..4d47150d6862 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts @@ -190,6 +190,21 @@ status = "okay"; }; +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + assigned-clocks = <&cru SCLK_PCIEPHY_REF>; + assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; + assigned-clock-rates = <100000000>; + ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + status = "okay"; +}; + &pinctrl { sdio-pwrseq { wifi_enable_h: wifi-enable-h { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi index e5b0369e197f..8c7db887f2cf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi @@ -471,21 +471,6 @@ gpio1830-supply = <&vcc_3v0>; }; -&pcie_phy { - status = "okay"; -}; - -&pcie0 { - assigned-clocks = <&cru SCLK_PCIEPHY_REF>; - assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; - assigned-clock-rates = <100000000>; - ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn_cpm>; - status = "okay"; -}; - &pmu_io_domains { pmu1830-supply = <&vcc_3v0>; status = "okay";