From patchwork Sun Jun 17 13:18:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 10468897 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 31D39600CC for ; Sun, 17 Jun 2018 13:20:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 13B4D2883A for ; Sun, 17 Jun 2018 13:20:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0582E288B9; Sun, 17 Jun 2018 13:20:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 49FA32883A for ; Sun, 17 Jun 2018 13:20:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=AWL7UAlBUhFYkxYNI3TowGcjHVISgLEqxBoWroLW6dM=; b=suC 749WeruqMqye+CZlEoPNqMwwGAHrG2YyYzhVHkGtYX6VJOGSLUGyZkgbmPNzivptB8vcYlpYQWjsY vzUAE3PBSglQXy77SyVmxvo/qXLhlGzhef1I/777EOd8ta/DoUJQerzcBCzRVv4l7Ug7lJfWtpXFp ODEHt5jcBgchX7iwk6Jj10gvCyOu5aEKc1kMBDCcexEPbu6i8m0suK8rStkEiRf99quplEloqLCjN x+p3/ZmknGhhko3kZmgXw211Qd1kP+ZHf8296TYs+O8YZ9JW4eLZLdbIwPsrJ+GZhxWO+DDr6jdM1 pQ5/lsgimiuB5fqY/H2/3O70sALIk+Q==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1fUXbl-0001hL-02; Sun, 17 Jun 2018 13:20:41 +0000 Received: from gloria.sntech.de ([95.129.55.99]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1fUXbh-0001gl-2s; Sun, 17 Jun 2018 13:20:39 +0000 Received: from x2f7fb73.dyn.telefonica.de ([2.247.251.115] helo=phil.sntech) by gloria.sntech.de with esmtpsa (TLS1.1:DHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1fUXbM-0004Lr-Ef; Sun, 17 Jun 2018 15:20:22 +0200 From: Heiko Stuebner To: linux-rockchip@lists.infradead.org Subject: [PATCH] ARM: dts: rockchip: convert rk3288 to operating-points-v2 Date: Sun, 17 Jun 2018 15:18:08 +0200 Message-Id: <20180617131808.30283-1-heiko@sntech.de> X-Mailer: git-send-email 2.17.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180617_062037_280365_566FDAE2 X-CRM114-Status: GOOD ( 11.97 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Heiko Stuebner , viresh.kumar@linaro.org, briannorris@chromium.org, dianders@chromium.org, linux-arm-kernel@lists.infradead.org, amstan@chromium.org MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Operating points need to be present in each cpu core using it, not only the first one. With operating-points-v1 this would require duplicating this table into each cpu node. With opp-v2 we can share the same table on all nodes. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron.dtsi | 36 +++++++------- arch/arm/boot/dts/rk3288.dtsi | 70 ++++++++++++++++++++++------ 2 files changed, 75 insertions(+), 31 deletions(-) diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 823c7ed47fcf..c8c83bf544b9 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -91,22 +91,26 @@ &cpu0 { cpu0-supply = <&vdd_cpu>; - operating-points = < - /* KHz uV */ - 1800000 1400000 - 1704000 1350000 - 1608000 1300000 - 1512000 1250000 - 1416000 1200000 - 1200000 1100000 - 1008000 1050000 - 816000 1000000 - 696000 950000 - 600000 900000 - 408000 900000 - 216000 900000 - 126000 900000 - >; +}; + +/* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */ +&cpu_opp_table { + /delete-node/ opp02; + + opp10 { + opp-microvolt = <1250000>; + }; + opp11 { + opp-microvolt = <1300000>; + }; + opp12 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <1350000>; + }; + opp13 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1400000>; + }; }; &emmc { diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 2a060c2dc383..a3af3f6ad8d0 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -60,21 +60,7 @@ compatible = "arm,cortex-a12"; reg = <0x500>; resets = <&cru SRST_CORE0>; - operating-points = < - /* KHz uV */ - 1608000 1350000 - 1512000 1300000 - 1416000 1200000 - 1200000 1100000 - 1008000 1050000 - 816000 1000000 - 696000 950000 - 600000 900000 - 408000 900000 - 312000 900000 - 216000 900000 - 126000 900000 - >; + operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ clock-latency = <40000>; clocks = <&cru ARMCLK>; @@ -99,6 +85,60 @@ }; }; + cpu_opp_table: cpu-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <126000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <216000000>; + opp-microvolt = <900000>; + }; + opp02 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <900000>; + }; + opp03 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <900000>; + }; + opp04 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000>; + }; + opp05 { + opp-hz = /bits/ 64 <696000000>; + opp-microvolt = <950000>; + }; + opp06 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000>; + }; + opp07 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1050000>; + }; + opp08 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + }; + opp09 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1200000>; + }; + opp10 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1300000>; + }; + opp11 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1350000>; + }; + }; + amba { compatible = "simple-bus"; #address-cells = <2>;