From patchwork Mon Aug 6 15:53:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Enric Balletbo i Serra X-Patchwork-Id: 10557351 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1002613AC for ; Mon, 6 Aug 2018 15:54:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F007B29251 for ; Mon, 6 Aug 2018 15:54:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E2C1F29683; Mon, 6 Aug 2018 15:54:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8F81929251 for ; Mon, 6 Aug 2018 15:54:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=aVypfWd7HBuBpxgk7+3YSI/XAKtyCjHjaujIOUVoZ2Q=; b=GixVxBwJBhDDTl ktALEk85vDlWYinZ96/JKZCyo2rHr0TArpTlhxSEez9p985O8XlfknanVPUE9VGBngF6OPQXyz+dU yyAi2hZK0PIHfeWUPYpdYzhnkZ9wxbhmBrd6A2n4H4Ck4NUyc9XWwAjkjxB9lqDpZy84V47+ElKTj cRDzCDYV+YtHhDPCZVGs/q2cHChDlmblp/diJFP59YKwpS+OpwTPlHzknK+fX4ZdAxKfu4+LUeQsT NjlBtN3Zp8HdxgFqBWouQSzIeAfuDq02yIqzO6m1R5ugo1RrQaxbNzOcqjFuSbuyBE1nHWGfG4zz7 9epMyzh3Td3AvCb+qUNA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1fmhpk-0002z5-Rg; Mon, 06 Aug 2018 15:54:12 +0000 Received: from bhuna.collabora.co.uk ([46.235.227.227]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1fmhpb-0002p2-Jh; Mon, 06 Aug 2018 15:54:05 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: eballetbo) with ESMTPSA id 505FA263981 From: Enric Balletbo i Serra To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , David Airlie Subject: [PATCH] drm/rockchip: update cursors asynchronously through atomic. Date: Mon, 6 Aug 2018 17:53:39 +0200 Message-Id: <20180806155339.9473-1-enric.balletbo@collabora.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180806_085403_923890_48622759 X-CRM114-Status: GOOD ( 12.57 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?St=C3=A9phane_Marchesin?= , Sean Paul , Gustavo Padovan , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Tomasz Figa , linux-rockchip@lists.infradead.org, kernel@collabora.com, linux-arm-kernel@lists.infradead.org Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add support to async updates of cursors by using the new atomic interface for that. Signed-off-by: Enric Balletbo i Serra --- Hi, This first version is slightly different from the RFC, note that I did not maintain the Sean reviewed tag for that reason. With this version I don't touch the atomic_update function and all is implemented in the async_check/update functions. See the changelog for a list of changes. The patch was tested on a Samsung Chromebook Plus in two ways. 1. Running all igt kms_cursor_legacy and kms_atomic@plane_cursor_legacy tests and see that there is no regression after the patch. 2. Running weston using the atomic API. Best regards, Enric Changes in v1: - Rebased on top of drm-misc - In async_check call drm_atomic_helper_check_plane_state to check that the desired plane is valid and update various bits of derived state (clipped coordinates etc.) - In async_check allow to configure new scaling in the fast path. - In async_update force to flush all registered PSR encoders. - In async_update call atomic_update directly. - In async_update call vop_cfg_done needed to set the vop registers and take effect. drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 53 +++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index e9f91278137d..dab70056ee73 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -811,10 +811,63 @@ static void vop_plane_atomic_update(struct drm_plane *plane, spin_unlock(&vop->reg_lock); } +static int vop_plane_atomic_async_check(struct drm_plane *plane, + struct drm_plane_state *state) +{ + struct vop_win *vop_win = to_vop_win(plane); + const struct vop_win_data *win = vop_win->data; + int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : + DRM_PLANE_HELPER_NO_SCALING; + int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : + DRM_PLANE_HELPER_NO_SCALING; + int ret; + + if (plane != state->crtc->cursor) + return -EINVAL; + + if (!plane->state) + return -EINVAL; + + if (!plane->state->fb || + plane->state->fb != state->fb) + return -EINVAL; + + ret = drm_atomic_helper_check_plane_state(plane->state, + plane->crtc->state, + min_scale, max_scale, + true, true); + return ret; +} + +static void vop_plane_atomic_async_update(struct drm_plane *plane, + struct drm_plane_state *new_state) +{ + struct vop *vop = to_vop(plane->state->crtc); + + plane->state->crtc_x = new_state->crtc_x; + plane->state->crtc_y = new_state->crtc_y; + plane->state->crtc_h = new_state->crtc_h; + plane->state->crtc_w = new_state->crtc_w; + plane->state->src_x = new_state->src_x; + plane->state->src_y = new_state->src_y; + plane->state->src_h = new_state->src_h; + plane->state->src_w = new_state->src_w; + + if (vop->is_enabled) { + rockchip_drm_psr_flush_all(plane->dev); + vop_plane_atomic_update(plane, plane->state); + spin_lock(&vop->reg_lock); + vop_cfg_done(vop); + spin_unlock(&vop->reg_lock); + } +} + static const struct drm_plane_helper_funcs plane_helper_funcs = { .atomic_check = vop_plane_atomic_check, .atomic_update = vop_plane_atomic_update, .atomic_disable = vop_plane_atomic_disable, + .atomic_async_check = vop_plane_atomic_async_check, + .atomic_async_update = vop_plane_atomic_async_update, }; static const struct drm_plane_funcs vop_plane_funcs = {