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Thu, 11 Apr 2019 11:49:06 -0700 (PDT) From: Tom Murphy To: iommu@lists.linux-foundation.org Subject: [PATCH 5/9] iommu/amd: Implement .flush_np_cache Date: Thu, 11 Apr 2019 19:47:34 +0100 Message-Id: <20190411184741.27540-6-tmurphy@arista.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190411184741.27540-1-tmurphy@arista.com> References: <20190411184741.27540-1-tmurphy@arista.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190411_114908_787282_5161B66B X-CRM114-Status: GOOD ( 13.15 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Heiko Stuebner , jamessewart@arista.com, Will Deacon , David Brown , Marek Szyprowski , linux-samsung-soc@vger.kernel.org, dima@arista.com, Joerg Roedel , Krzysztof Kozlowski , linux-rockchip@lists.infradead.org, Kukjin Kim , Andy Gross , Marc Zyngier , linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, Matthias Brugger , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Tom Murphy , linux-kernel@vger.kernel.org, murphyt7@tcd.ie, Rob Clark , Robin Murphy MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Implement flush_np_cache for the AMD iommu driver. This allows the amd iommu non present cache to be flushed if amd_iommu_np_cache is set. Signed-off-by: Tom Murphy --- drivers/iommu/amd_iommu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c index b319e51c379b..2d4ee10626b4 100644 --- a/drivers/iommu/amd_iommu.c +++ b/drivers/iommu/amd_iommu.c @@ -1319,6 +1319,18 @@ static void domain_flush_devices(struct protection_domain *domain) device_flush_dte(dev_data); } +static void amd_iommu_flush_np_cache(struct iommu_domain *domain, + unsigned long iova, size_t size) +{ + struct protection_domain *dom = to_pdomain(domain); + + if (unlikely(amd_iommu_np_cache)) { + domain_flush_pages(dom, iova, size); + domain_flush_complete(dom); + } +} + + /**************************************************************************** * * The functions below are used the create the page table mappings for @@ -3263,6 +3275,7 @@ const struct iommu_ops amd_iommu_ops = { .flush_iotlb_all = amd_iommu_flush_iotlb_all, .iotlb_range_add = amd_iommu_iotlb_range_add, .iotlb_sync = amd_iommu_flush_iotlb_all, + .flush_np_cache = amd_iommu_flush_np_cache, }; /*****************************************************************************