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Papadakos" To: Rob Herring , Heiko Stuebner , Jose Abreu , Robin Murphy Subject: [PATCH] arm64: dts: rockchip: set TX PBL for rk3328-roc-cc gmac Date: Thu, 18 Apr 2019 00:01:00 +0300 Message-Id: <20190417210059.26262-1-papadakospan@gmail.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190417_140133_266354_DBFA55D7 X-CRM114-Status: GOOD ( 12.43 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "Leonidas P. Papadakos" , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Some rockchip boards have issues with tx checksumming for packets larger than 1498 B. An iperf test will tell you that transmissions stop almost immediately. A workaround to this issue is disabling TX checksumming offload, and one of the ways to do that is snps,force_thresh_dma_mode. But after some discussion here it seems there is another path: https://lkml.org/lkml/2019/4/5/148 Setting txpbl is a better-performing (maybe temporary) solution compared to disabling T offload. In my testing with a Libre Computer Renegade, this was the best all-around option, and increasing the MTU doesn't cause a queue timeout anymore. Signed-off-by: Leonidas P. Papadakos --- arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts index 5d499c908..974f2dcdf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts @@ -141,10 +141,10 @@ phy-mode = "rgmii"; pinctrl-names = "default"; pinctrl-0 = <&rgmiim1_pins>; - snps,force_thresh_dma_mode; snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; snps,reset-active-low; snps,reset-delays-us = <0 10000 50000>; + snps,txpbl = <0x4>; tx_delay = <0x24>; rx_delay = <0x18>; status = "okay";