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Thu, 16 May 2019 21:06:43 -0700 (PDT) From: Manivannan Sadhasivam To: heiko@sntech.de Subject: [PATCH v2 2/2] arm64: dts: rockchip: Enable SPI1 on Ficus Date: Fri, 17 May 2019 09:36:25 +0530 Message-Id: <20190517040625.14607-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190517040625.14607-1-manivannan.sadhasivam@linaro.org> References: <20190517040625.14607-1-manivannan.sadhasivam@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190516_210645_824496_2CCE5645 X-CRM114-Status: GOOD ( 10.18 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tom@vamrs.com, linux-kernel@vger.kernel.org, dev@vamrs.com, linux-rockchip@lists.infradead.org, Manivannan Sadhasivam , ezequiel@collabora.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Enable SPI1 exposed on both Low and High speed expansion connectors of Ficus. SPI1 has 3 different chip selects wired as below: CS0 - Serial Flash (unpopulated) CS1 - Low Speed expansion CS2 - High Speed expansion Signed-off-by: Manivannan Sadhasivam --- Changes in v2: * Used pin constants instead of hardcoding cs-gpios arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts index 027d428917b8..9af02d859dcd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts @@ -146,6 +146,12 @@ }; }; +&spi1 { + /* On both Low speed and High speed expansion */ + cs-gpios = <0>, <&gpio4 RK_PA6 0>, <&gpio4 RK_PA7 0>; + status = "okay"; +}; + &usbdrd_dwc3_0 { dr_mode = "host"; };