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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1ipIaF-00028n-AH; Wed, 08 Jan 2020 21:09:43 +0000 Received: from o1.b.az.sendgrid.net ([208.117.55.133]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1ipIYQ-0000BA-KQ for linux-rockchip@lists.infradead.org; Wed, 08 Jan 2020 21:07:57 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=from:subject:in-reply-to:references:to:cc:content-type: content-transfer-encoding; s=001; bh=nAJZakghzr7JwdXt31dydBHC6AGXJnAIYTAyCKaQf5U=; b=olAzvIXs+468+uJpM5hc9UydRh8zXgV6l5BJ4Pu4pnK0qL8HTi7bwAV/YQ5/SYgrU7If dKnjrsmOOl0+OpQeFTGvu5RKryBjI3l4wLZ7D5dO9g9zH10LNcUmD6kEs1H+6S5/0wbmOo RPQUEcWbTxMC0Q2BRp2gq6JrANlf+CzXQ= Received: by filterdrecv-p3mdw1-56c97568b5-bbmbb with SMTP id filterdrecv-p3mdw1-56c97568b5-bbmbb-18-5E1644A5-10 2020-01-08 21:07:49.289120385 +0000 UTC m=+1974277.925691392 Received: from bionic.localdomain (unknown [98.128.173.80]) by ismtpd0005p1lon1.sendgrid.net (SG) with ESMTP id QpQFtE6kTYGCgtswu4iudQ Wed, 08 Jan 2020 21:07:49.090 +0000 (UTC) From: Jonas Karlman Subject: [PATCH v2 05/14] phy/rockchip: inno-hdmi: force set_rate on power_on Date: Wed, 08 Jan 2020 21:07:49 +0000 (UTC) Message-Id: <20200108210740.28769-6-jonas@kwiboo.se> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200108210740.28769-1-jonas@kwiboo.se> References: <20200108210740.28769-1-jonas@kwiboo.se> X-SG-EID: TdbjyGynYnRZWhH+7lKUQJL+ZxmxpowvO2O9SQF5CwCVrYgcwUXgU5DKUU3QxAfZekEeQsTe+RrMu3cja6a0h/7F4adz3wm6ffQRTCTgb+AFqFhunflnZfCfUag8AxDjwfbQB0Wd5domN1gIXRXtJdfpmpEbksvt+sFcrrxsghs7sWTJccsN4oHoZIqqdUY9HylwKKLktSCut/3Ic/PICFXGQchntyTdjSjkapBox1YT7j9pBi1Xehf33BA1mV5JCjcaLtdpUfJCjxFNRI2QYQ== To: Heiko Stuebner , Sandy Huang X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200108_130750_786627_06952105 X-CRM114-Status: GOOD ( 10.65 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [208.117.55.133 listed in wl.mailspike.net] -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [208.117.55.133 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jonas Karlman , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Kishon Vijay Abraham I , linux-rockchip@lists.infradead.org, Huicong Xu , linux-arm-kernel@lists.infradead.org, Zheng Yang MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org From: Huicong Xu Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and not in pixel clock rate. When the hdmiphy clock is configured with the same pixel clock rate using clk_set_rate() the clock framework do not signal the hdmi phy driver to set_rate when switching between 8-bit and Deep Color. This result in pre/post pll not being re-configured when switching between regular 8-bit and Deep Color video formats. Fix this by calling set_rate in power_on to force pre pll re-configuration. Signed-off-by: Huicong Xu Signed-off-by: Jonas Karlman --- drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c index 3a59a6da0440..3719309ad0d0 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c @@ -245,6 +245,7 @@ struct inno_hdmi_phy { struct clk_hw hw; struct clk *phyclk; unsigned long pixclock; + unsigned long tmdsclock; }; struct pre_pll_config { @@ -485,6 +486,8 @@ static int inno_hdmi_phy_power_on(struct phy *phy) dev_dbg(inno->dev, "Inno HDMI PHY Power On\n"); + inno->plat_data->clk_ops->set_rate(&inno->hw, inno->pixclock, 24000000); + ret = clk_prepare_enable(inno->phyclk); if (ret) return ret; @@ -509,6 +512,8 @@ static int inno_hdmi_phy_power_off(struct phy *phy) clk_disable_unprepare(inno->phyclk); + inno->tmdsclock = 0; + dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n"); return 0; @@ -628,6 +633,9 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw, dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", __func__, rate, tmdsclock); + if (inno->pixclock == rate && inno->tmdsclock == tmdsclock) + return 0; + cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate); if (IS_ERR(cfg)) return PTR_ERR(cfg); @@ -670,6 +678,7 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw, } inno->pixclock = rate; + inno->tmdsclock = tmdsclock; return 0; } @@ -781,6 +790,9 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw, dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", __func__, rate, tmdsclock); + if (inno->pixclock == rate && inno->tmdsclock == tmdsclock) + return 0; + cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate); if (IS_ERR(cfg)) return PTR_ERR(cfg); @@ -820,6 +832,7 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw, } inno->pixclock = rate; + inno->tmdsclock = tmdsclock; return 0; }