diff mbox series

[v2,1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls

Message ID 20200903063147.10237-2-zhangqing@rock-chips.com
State New
Headers show
Series clk: rockchip: Support module build | expand

Commit Message

Elaine Zhang Sept. 3, 2020, 6:31 a.m. UTC
clk_hw_register_composite it's already exported.
Preparation for compilation of rK common clock drivers into modules.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk-half-divider.c | 18 ++++----
 drivers/clk/rockchip/clk.c              | 58 ++++++++++++-------------
 2 files changed, 38 insertions(+), 38 deletions(-)

Comments

Kever Yang Sept. 3, 2020, 10:02 a.m. UTC | #1
Hi Elaine,

On 2020/9/3 下午2:31, Elaine Zhang wrote:
> clk_hw_register_composite it's already exported.
> Preparation for compilation of rK common clock drivers into modules.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
>   drivers/clk/rockchip/clk-half-divider.c | 18 ++++----
>   drivers/clk/rockchip/clk.c              | 58 ++++++++++++-------------
>   2 files changed, 38 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk-half-divider.c b/drivers/clk/rockchip/clk-half-divider.c
> index b333fc28c94b..e97fd3dfbae7 100644
> --- a/drivers/clk/rockchip/clk-half-divider.c
> +++ b/drivers/clk/rockchip/clk-half-divider.c
> @@ -166,7 +166,7 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
>   					  unsigned long flags,
>   					  spinlock_t *lock)
>   {
> -	struct clk *clk;
> +	struct clk_hw *hw;
>   	struct clk_mux *mux = NULL;
>   	struct clk_gate *gate = NULL;
>   	struct clk_divider *div = NULL;
> @@ -212,16 +212,18 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
>   		div_ops = &clk_half_divider_ops;
>   	}
>   
> -	clk = clk_register_composite(NULL, name, parent_names, num_parents,
> -				     mux ? &mux->hw : NULL, mux_ops,
> -				     div ? &div->hw : NULL, div_ops,
> -				     gate ? &gate->hw : NULL, gate_ops,
> -				     flags);
> +	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
> +				       mux ? &mux->hw : NULL, mux_ops,
> +				       div ? &div->hw : NULL, div_ops,
> +				       gate ? &gate->hw : NULL, gate_ops,
> +				       flags);
> +	if (IS_ERR(hw))
> +		goto err_div;
>   
> -	return clk;
> +	return hw->clk;
>   err_div:
>   	kfree(gate);
>   err_gate:
>   	kfree(mux);
> -	return ERR_PTR(-ENOMEM);
> +	return ERR_CAST(hw);
>   }
> diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
> index 546e810c3560..b51f320e5733 100644
> --- a/drivers/clk/rockchip/clk.c
> +++ b/drivers/clk/rockchip/clk.c
> @@ -43,7 +43,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
>   		u8 gate_shift, u8 gate_flags, unsigned long flags,
>   		spinlock_t *lock)
>   {
> -	struct clk *clk;
> +	struct clk_hw *hw;
>   	struct clk_mux *mux = NULL;
>   	struct clk_gate *gate = NULL;
>   	struct clk_divider *div = NULL;
> @@ -100,25 +100,22 @@ static struct clk *rockchip_clk_register_branch(const char *name,
>   						: &clk_divider_ops;
>   	}
>   
> -	clk = clk_register_composite(NULL, name, parent_names, num_parents,
> -				     mux ? &mux->hw : NULL, mux_ops,
> -				     div ? &div->hw : NULL, div_ops,
> -				     gate ? &gate->hw : NULL, gate_ops,
> -				     flags);
> -
> -	if (IS_ERR(clk)) {
> -		ret = PTR_ERR(clk);
> +	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
> +				       mux ? &mux->hw : NULL, mux_ops,
> +				       div ? &div->hw : NULL, div_ops,
> +				       gate ? &gate->hw : NULL, gate_ops,
> +				       flags);
> +	if (IS_ERR(hw))
>   		goto err_composite;
> -	}
>   
> -	return clk;
> +	return hw->clk;
>   err_composite:
>   	kfree(div);
>   err_div:
>   	kfree(gate);
>   err_gate:
>   	kfree(mux);
> -	return ERR_PTR(ret);
> +	return ERR_CAST(hw);
>   }
>   
>   struct rockchip_clk_frac {
> @@ -214,8 +211,8 @@ static struct clk *rockchip_clk_register_frac_branch(
>   		unsigned long flags, struct rockchip_clk_branch *child,
>   		spinlock_t *lock)
>   {
> +	struct clk_hw *hw;
>   	struct rockchip_clk_frac *frac;
> -	struct clk *clk;
>   	struct clk_gate *gate = NULL;
>   	struct clk_fractional_divider *div = NULL;
>   	const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
> @@ -255,14 +252,14 @@ static struct clk *rockchip_clk_register_frac_branch(
>   	div->approximation = rockchip_fractional_approximation;
>   	div_ops = &clk_fractional_divider_ops;
>   
> -	clk = clk_register_composite(NULL, name, parent_names, num_parents,
> -				     NULL, NULL,
> -				     &div->hw, div_ops,
> -				     gate ? &gate->hw : NULL, gate_ops,
> -				     flags | CLK_SET_RATE_UNGATE);
> -	if (IS_ERR(clk)) {
> +	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
> +				       NULL, NULL,
> +				       &div->hw, div_ops,
> +				       gate ? &gate->hw : NULL, gate_ops,
> +				       flags | CLK_SET_RATE_UNGATE);
> +	if (IS_ERR(hw)) {
>   		kfree(frac);
> -		return clk;
> +		return ERR_CAST(hw);
>   	}
>   
>   	if (child) {
> @@ -292,7 +289,7 @@ static struct clk *rockchip_clk_register_frac_branch(
>   		mux_clk = clk_register(NULL, &frac_mux->hw);
>   		if (IS_ERR(mux_clk)) {
>   			kfree(frac);
> -			return clk;
> +			return mux_clk;
>   		}
>   
>   		rockchip_clk_add_lookup(ctx, mux_clk, child->id);
> @@ -301,7 +298,7 @@ static struct clk *rockchip_clk_register_frac_branch(
>   		if (frac->mux_frac_idx >= 0) {
>   			pr_debug("%s: found fractional parent in mux at pos %d\n",
>   				 __func__, frac->mux_frac_idx);
> -			ret = clk_notifier_register(clk, &frac->clk_nb);
> +			ret = clk_notifier_register(hw->clk, &frac->clk_nb);
>   			if (ret)
>   				pr_err("%s: failed to register clock notifier for %s\n",
>   						__func__, name);
> @@ -311,7 +308,7 @@ static struct clk *rockchip_clk_register_frac_branch(
>   		}
>   	}
>   
> -	return clk;
> +	return hw->clk;
>   }
>   
>   static struct clk *rockchip_clk_register_factor_branch(const char *name,
> @@ -320,7 +317,7 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
>   		int gate_offset, u8 gate_shift, u8 gate_flags,
>   		unsigned long flags, spinlock_t *lock)
>   {
> -	struct clk *clk;
> +	struct clk_hw *hw;
>   	struct clk_gate *gate = NULL;
>   	struct clk_fixed_factor *fix = NULL;
>   
> @@ -349,16 +346,17 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
>   	fix->mult = mult;
>   	fix->div = div;
>   
> -	clk = clk_register_composite(NULL, name, parent_names, num_parents,
> -				     NULL, NULL,
> -				     &fix->hw, &clk_fixed_factor_ops,
> -				     &gate->hw, &clk_gate_ops, flags);
> -	if (IS_ERR(clk)) {
> +	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
> +				       NULL, NULL,
> +				       &fix->hw, &clk_fixed_factor_ops,
> +				       &gate->hw, &clk_gate_ops, flags);
> +	if (IS_ERR(hw)) {
>   		kfree(fix);
>   		kfree(gate);
> +		return ERR_CAST(hw);
>   	}
>   
> -	return clk;
> +	return hw->clk;
>   }
>   
>   struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,

This looks good to me, so

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,

- Kever
kernel test robot Sept. 3, 2020, 12:30 p.m. UTC | #2
Hi Elaine,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on rockchip/for-next]
[also build test WARNING on clk/clk-next v5.9-rc3 next-20200903]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Elaine-Zhang/clk-rockchip-Support-module-build/20200903-143443
base:   https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next
config: arm64-randconfig-r014-20200902 (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   drivers/clk/rockchip/clk.c: In function 'rockchip_clk_register_branch':
>> drivers/clk/rockchip/clk.c:52:6: warning: variable 'ret' set but not used [-Wunused-but-set-variable]
      52 |  int ret;
         |      ^~~

# https://github.com/0day-ci/linux/commit/47a0fbff201df1b9022204113caca1ed6da700b1
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Elaine-Zhang/clk-rockchip-Support-module-build/20200903-143443
git checkout 47a0fbff201df1b9022204113caca1ed6da700b1
vim +/ret +52 drivers/clk/rockchip/clk.c

a245fecbb80646 Heiko Stübner  2014-07-03   26  
a245fecbb80646 Heiko Stübner  2014-07-03   27  /**
a245fecbb80646 Heiko Stübner  2014-07-03   28   * Register a clock branch.
a245fecbb80646 Heiko Stübner  2014-07-03   29   * Most clock branches have a form like
a245fecbb80646 Heiko Stübner  2014-07-03   30   *
a245fecbb80646 Heiko Stübner  2014-07-03   31   * src1 --|--\
a245fecbb80646 Heiko Stübner  2014-07-03   32   *        |M |--[GATE]-[DIV]-
a245fecbb80646 Heiko Stübner  2014-07-03   33   * src2 --|--/
a245fecbb80646 Heiko Stübner  2014-07-03   34   *
a245fecbb80646 Heiko Stübner  2014-07-03   35   * sometimes without one of those components.
a245fecbb80646 Heiko Stübner  2014-07-03   36   */
1a4b1819950a27 Heiko Stübner  2014-08-27   37  static struct clk *rockchip_clk_register_branch(const char *name,
03ae1747869437 Heiko Stuebner 2016-04-19   38  		const char *const *parent_names, u8 num_parents,
03ae1747869437 Heiko Stuebner 2016-04-19   39  		void __iomem *base,
a245fecbb80646 Heiko Stübner  2014-07-03   40  		int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
1f55660ff80522 Finley Xiao    2019-04-03   41  		int div_offset, u8 div_shift, u8 div_width, u8 div_flags,
a245fecbb80646 Heiko Stübner  2014-07-03   42  		struct clk_div_table *div_table, int gate_offset,
a245fecbb80646 Heiko Stübner  2014-07-03   43  		u8 gate_shift, u8 gate_flags, unsigned long flags,
a245fecbb80646 Heiko Stübner  2014-07-03   44  		spinlock_t *lock)
a245fecbb80646 Heiko Stübner  2014-07-03   45  {
47a0fbff201df1 Elaine Zhang   2020-09-03   46  	struct clk_hw *hw;
a245fecbb80646 Heiko Stübner  2014-07-03   47  	struct clk_mux *mux = NULL;
a245fecbb80646 Heiko Stübner  2014-07-03   48  	struct clk_gate *gate = NULL;
a245fecbb80646 Heiko Stübner  2014-07-03   49  	struct clk_divider *div = NULL;
a245fecbb80646 Heiko Stübner  2014-07-03   50  	const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
a245fecbb80646 Heiko Stübner  2014-07-03   51  			     *gate_ops = NULL;
fd3cbbfb76a422 Shawn Lin      2018-02-28  @52  	int ret;
a245fecbb80646 Heiko Stübner  2014-07-03   53  
a245fecbb80646 Heiko Stübner  2014-07-03   54  	if (num_parents > 1) {
a245fecbb80646 Heiko Stübner  2014-07-03   55  		mux = kzalloc(sizeof(*mux), GFP_KERNEL);
a245fecbb80646 Heiko Stübner  2014-07-03   56  		if (!mux)
a245fecbb80646 Heiko Stübner  2014-07-03   57  			return ERR_PTR(-ENOMEM);
a245fecbb80646 Heiko Stübner  2014-07-03   58  
a245fecbb80646 Heiko Stübner  2014-07-03   59  		mux->reg = base + muxdiv_offset;
a245fecbb80646 Heiko Stübner  2014-07-03   60  		mux->shift = mux_shift;
a245fecbb80646 Heiko Stübner  2014-07-03   61  		mux->mask = BIT(mux_width) - 1;
a245fecbb80646 Heiko Stübner  2014-07-03   62  		mux->flags = mux_flags;
a245fecbb80646 Heiko Stübner  2014-07-03   63  		mux->lock = lock;
a245fecbb80646 Heiko Stübner  2014-07-03   64  		mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
a245fecbb80646 Heiko Stübner  2014-07-03   65  							: &clk_mux_ops;
a245fecbb80646 Heiko Stübner  2014-07-03   66  	}
a245fecbb80646 Heiko Stübner  2014-07-03   67  
a245fecbb80646 Heiko Stübner  2014-07-03   68  	if (gate_offset >= 0) {
a245fecbb80646 Heiko Stübner  2014-07-03   69  		gate = kzalloc(sizeof(*gate), GFP_KERNEL);
fd3cbbfb76a422 Shawn Lin      2018-02-28   70  		if (!gate) {
fd3cbbfb76a422 Shawn Lin      2018-02-28   71  			ret = -ENOMEM;
2467b6745e0ae9 Shawn Lin      2016-02-02   72  			goto err_gate;
fd3cbbfb76a422 Shawn Lin      2018-02-28   73  		}
a245fecbb80646 Heiko Stübner  2014-07-03   74  
a245fecbb80646 Heiko Stübner  2014-07-03   75  		gate->flags = gate_flags;
a245fecbb80646 Heiko Stübner  2014-07-03   76  		gate->reg = base + gate_offset;
a245fecbb80646 Heiko Stübner  2014-07-03   77  		gate->bit_idx = gate_shift;
a245fecbb80646 Heiko Stübner  2014-07-03   78  		gate->lock = lock;
a245fecbb80646 Heiko Stübner  2014-07-03   79  		gate_ops = &clk_gate_ops;
a245fecbb80646 Heiko Stübner  2014-07-03   80  	}
a245fecbb80646 Heiko Stübner  2014-07-03   81  
a245fecbb80646 Heiko Stübner  2014-07-03   82  	if (div_width > 0) {
a245fecbb80646 Heiko Stübner  2014-07-03   83  		div = kzalloc(sizeof(*div), GFP_KERNEL);
fd3cbbfb76a422 Shawn Lin      2018-02-28   84  		if (!div) {
fd3cbbfb76a422 Shawn Lin      2018-02-28   85  			ret = -ENOMEM;
2467b6745e0ae9 Shawn Lin      2016-02-02   86  			goto err_div;
fd3cbbfb76a422 Shawn Lin      2018-02-28   87  		}
a245fecbb80646 Heiko Stübner  2014-07-03   88  
a245fecbb80646 Heiko Stübner  2014-07-03   89  		div->flags = div_flags;
1f55660ff80522 Finley Xiao    2019-04-03   90  		if (div_offset)
1f55660ff80522 Finley Xiao    2019-04-03   91  			div->reg = base + div_offset;
1f55660ff80522 Finley Xiao    2019-04-03   92  		else
a245fecbb80646 Heiko Stübner  2014-07-03   93  			div->reg = base + muxdiv_offset;
a245fecbb80646 Heiko Stübner  2014-07-03   94  		div->shift = div_shift;
a245fecbb80646 Heiko Stübner  2014-07-03   95  		div->width = div_width;
a245fecbb80646 Heiko Stübner  2014-07-03   96  		div->lock = lock;
a245fecbb80646 Heiko Stübner  2014-07-03   97  		div->table = div_table;
50359819794b4a Heiko Stuebner 2016-01-21   98  		div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
50359819794b4a Heiko Stuebner 2016-01-21   99  						? &clk_divider_ro_ops
50359819794b4a Heiko Stuebner 2016-01-21  100  						: &clk_divider_ops;
a245fecbb80646 Heiko Stübner  2014-07-03  101  	}
a245fecbb80646 Heiko Stübner  2014-07-03  102  
47a0fbff201df1 Elaine Zhang   2020-09-03  103  	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
a245fecbb80646 Heiko Stübner  2014-07-03  104  				       mux ? &mux->hw : NULL, mux_ops,
a245fecbb80646 Heiko Stübner  2014-07-03  105  				       div ? &div->hw : NULL, div_ops,
a245fecbb80646 Heiko Stübner  2014-07-03  106  				       gate ? &gate->hw : NULL, gate_ops,
a245fecbb80646 Heiko Stübner  2014-07-03  107  				       flags);
47a0fbff201df1 Elaine Zhang   2020-09-03  108  	if (IS_ERR(hw))
fd3cbbfb76a422 Shawn Lin      2018-02-28  109  		goto err_composite;
fd3cbbfb76a422 Shawn Lin      2018-02-28  110  
47a0fbff201df1 Elaine Zhang   2020-09-03  111  	return hw->clk;
fd3cbbfb76a422 Shawn Lin      2018-02-28  112  err_composite:
fd3cbbfb76a422 Shawn Lin      2018-02-28  113  	kfree(div);
2467b6745e0ae9 Shawn Lin      2016-02-02  114  err_div:
2467b6745e0ae9 Shawn Lin      2016-02-02  115  	kfree(gate);
2467b6745e0ae9 Shawn Lin      2016-02-02  116  err_gate:
2467b6745e0ae9 Shawn Lin      2016-02-02  117  	kfree(mux);
47a0fbff201df1 Elaine Zhang   2020-09-03  118  	return ERR_CAST(hw);
a245fecbb80646 Heiko Stübner  2014-07-03  119  }
a245fecbb80646 Heiko Stübner  2014-07-03  120  

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
diff mbox series

Patch

diff --git a/drivers/clk/rockchip/clk-half-divider.c b/drivers/clk/rockchip/clk-half-divider.c
index b333fc28c94b..e97fd3dfbae7 100644
--- a/drivers/clk/rockchip/clk-half-divider.c
+++ b/drivers/clk/rockchip/clk-half-divider.c
@@ -166,7 +166,7 @@  struct clk *rockchip_clk_register_halfdiv(const char *name,
 					  unsigned long flags,
 					  spinlock_t *lock)
 {
-	struct clk *clk;
+	struct clk_hw *hw;
 	struct clk_mux *mux = NULL;
 	struct clk_gate *gate = NULL;
 	struct clk_divider *div = NULL;
@@ -212,16 +212,18 @@  struct clk *rockchip_clk_register_halfdiv(const char *name,
 		div_ops = &clk_half_divider_ops;
 	}
 
-	clk = clk_register_composite(NULL, name, parent_names, num_parents,
-				     mux ? &mux->hw : NULL, mux_ops,
-				     div ? &div->hw : NULL, div_ops,
-				     gate ? &gate->hw : NULL, gate_ops,
-				     flags);
+	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+				       mux ? &mux->hw : NULL, mux_ops,
+				       div ? &div->hw : NULL, div_ops,
+				       gate ? &gate->hw : NULL, gate_ops,
+				       flags);
+	if (IS_ERR(hw))
+		goto err_div;
 
-	return clk;
+	return hw->clk;
 err_div:
 	kfree(gate);
 err_gate:
 	kfree(mux);
-	return ERR_PTR(-ENOMEM);
+	return ERR_CAST(hw);
 }
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 546e810c3560..b51f320e5733 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -43,7 +43,7 @@  static struct clk *rockchip_clk_register_branch(const char *name,
 		u8 gate_shift, u8 gate_flags, unsigned long flags,
 		spinlock_t *lock)
 {
-	struct clk *clk;
+	struct clk_hw *hw;
 	struct clk_mux *mux = NULL;
 	struct clk_gate *gate = NULL;
 	struct clk_divider *div = NULL;
@@ -100,25 +100,22 @@  static struct clk *rockchip_clk_register_branch(const char *name,
 						: &clk_divider_ops;
 	}
 
-	clk = clk_register_composite(NULL, name, parent_names, num_parents,
-				     mux ? &mux->hw : NULL, mux_ops,
-				     div ? &div->hw : NULL, div_ops,
-				     gate ? &gate->hw : NULL, gate_ops,
-				     flags);
-
-	if (IS_ERR(clk)) {
-		ret = PTR_ERR(clk);
+	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+				       mux ? &mux->hw : NULL, mux_ops,
+				       div ? &div->hw : NULL, div_ops,
+				       gate ? &gate->hw : NULL, gate_ops,
+				       flags);
+	if (IS_ERR(hw))
 		goto err_composite;
-	}
 
-	return clk;
+	return hw->clk;
 err_composite:
 	kfree(div);
 err_div:
 	kfree(gate);
 err_gate:
 	kfree(mux);
-	return ERR_PTR(ret);
+	return ERR_CAST(hw);
 }
 
 struct rockchip_clk_frac {
@@ -214,8 +211,8 @@  static struct clk *rockchip_clk_register_frac_branch(
 		unsigned long flags, struct rockchip_clk_branch *child,
 		spinlock_t *lock)
 {
+	struct clk_hw *hw;
 	struct rockchip_clk_frac *frac;
-	struct clk *clk;
 	struct clk_gate *gate = NULL;
 	struct clk_fractional_divider *div = NULL;
 	const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
@@ -255,14 +252,14 @@  static struct clk *rockchip_clk_register_frac_branch(
 	div->approximation = rockchip_fractional_approximation;
 	div_ops = &clk_fractional_divider_ops;
 
-	clk = clk_register_composite(NULL, name, parent_names, num_parents,
-				     NULL, NULL,
-				     &div->hw, div_ops,
-				     gate ? &gate->hw : NULL, gate_ops,
-				     flags | CLK_SET_RATE_UNGATE);
-	if (IS_ERR(clk)) {
+	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+				       NULL, NULL,
+				       &div->hw, div_ops,
+				       gate ? &gate->hw : NULL, gate_ops,
+				       flags | CLK_SET_RATE_UNGATE);
+	if (IS_ERR(hw)) {
 		kfree(frac);
-		return clk;
+		return ERR_CAST(hw);
 	}
 
 	if (child) {
@@ -292,7 +289,7 @@  static struct clk *rockchip_clk_register_frac_branch(
 		mux_clk = clk_register(NULL, &frac_mux->hw);
 		if (IS_ERR(mux_clk)) {
 			kfree(frac);
-			return clk;
+			return mux_clk;
 		}
 
 		rockchip_clk_add_lookup(ctx, mux_clk, child->id);
@@ -301,7 +298,7 @@  static struct clk *rockchip_clk_register_frac_branch(
 		if (frac->mux_frac_idx >= 0) {
 			pr_debug("%s: found fractional parent in mux at pos %d\n",
 				 __func__, frac->mux_frac_idx);
-			ret = clk_notifier_register(clk, &frac->clk_nb);
+			ret = clk_notifier_register(hw->clk, &frac->clk_nb);
 			if (ret)
 				pr_err("%s: failed to register clock notifier for %s\n",
 						__func__, name);
@@ -311,7 +308,7 @@  static struct clk *rockchip_clk_register_frac_branch(
 		}
 	}
 
-	return clk;
+	return hw->clk;
 }
 
 static struct clk *rockchip_clk_register_factor_branch(const char *name,
@@ -320,7 +317,7 @@  static struct clk *rockchip_clk_register_factor_branch(const char *name,
 		int gate_offset, u8 gate_shift, u8 gate_flags,
 		unsigned long flags, spinlock_t *lock)
 {
-	struct clk *clk;
+	struct clk_hw *hw;
 	struct clk_gate *gate = NULL;
 	struct clk_fixed_factor *fix = NULL;
 
@@ -349,16 +346,17 @@  static struct clk *rockchip_clk_register_factor_branch(const char *name,
 	fix->mult = mult;
 	fix->div = div;
 
-	clk = clk_register_composite(NULL, name, parent_names, num_parents,
-				     NULL, NULL,
-				     &fix->hw, &clk_fixed_factor_ops,
-				     &gate->hw, &clk_gate_ops, flags);
-	if (IS_ERR(clk)) {
+	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+				       NULL, NULL,
+				       &fix->hw, &clk_fixed_factor_ops,
+				       &gate->hw, &clk_gate_ops, flags);
+	if (IS_ERR(hw)) {
 		kfree(fix);
 		kfree(gate);
+		return ERR_CAST(hw);
 	}
 
-	return clk;
+	return hw->clk;
 }
 
 struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,