| Message ID | 20201201160613.1419-1-vicencb@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3] drm: rockchip: hdmi: enable higher resolutions than FHD | expand |
On Tue, Dec 1, 2020 at 5:06 PM Vicente Bergas <vicencb@gmail.com> wrote:
> This patch enables a QHD HDMI monitor to work at native resolution.
Please, anybody?
On 2020-12-14 11:03, Vicente Bergas wrote: > On Tue, Dec 1, 2020 at 5:06 PM Vicente Bergas <vicencb@gmail.com> wrote: >> This patch enables a QHD HDMI monitor to work at native resolution. > > Please, anybody? Has anyone been able to validate this on other SoCs? I guess that's still the main concern - empirically I've found that clock rates that work perfectly on RK3399 can be glitchy on RK3288 to the point of being barely usable, and can result in no display at all on chips not using the Synopsys phy, like RK3328, where the HDMI driver considers the mode valid but later the phy driver is unable to match it. I don't have access to a QHD display to test this myself; I've only played around with weirder 4:3, 5:4 and 16:10 modes on PC monitors. Robin.
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 23de359a1..e1515d55b 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -148,6 +148,10 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { { 0x214c, 0x0003}, { 0x4064, 0x0003} }, + }, { + 241500000, { + { 0x0040, 0x0003}, + }, }, { ~0UL, { { 0x00a0, 0x000a }, @@ -173,6 +177,8 @@ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { 146250000, { 0x0038, 0x0038, 0x0038 }, }, { 148500000, { 0x0000, 0x0038, 0x0038 }, + }, { + 241500000, { 0x0000, }, }, { ~0UL, { 0x0000, 0x0000, 0x0000}, }
This patch enables a QHD HDMI monitor to work at native resolution. Tested on a Sapphire board with RK3399 connected to a Q27q-10 monitor at 2560x1440@60 Messages like dwhdmi-rockchip ff940000.hdmi: PHY configuration failed (clock 148501000) and like dwhdmi-rockchip ff940000.hdmi: PHY configuration failed (clock 241501000) were present and still are because of vop_crtc_mode_fixup in drivers/gpu/drm/rockchip/rockchip_drm_vop.c but this time the display ends up working fine, just after an extra delay of a few seconds. Changes since v2: Just add the strictly required frequency for backwards compatibility. Changes since v1: Use alternative clock rounding code proposed by Doug Anderson Signed-off-by: Vicente Bergas <vicencb@gmail.com> --- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 6 ++++++ 1 file changed, 6 insertions(+)