diff mbox series

[2/3] dt-bindings: rockchip: Add DesignWare based PCIe controller

Message ID 20210118091739.247040-2-xxm@rock-chips.com (mailing list archive)
State New
Headers show
Series [1/3] PCI: dwc: Skip allocating own MSI domain if using external MSI domain | expand

Commit Message

Simon Xue Jan. 18, 2021, 9:17 a.m. UTC
Signed-off-by: Simon Xue <xxm@rock-chips.com>
---
 .../bindings/pci/rockchip-dw-pcie.yaml        | 101 ++++++++++++++++++
 1 file changed, 101 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml

Comments

Johan Jonker Jan. 19, 2021, 1:07 p.m. UTC | #1
Hi Simon,

Thank you for this patch for rk3568 pcie.

Include the Rockchip device tree maintainer and all other people/lists
to the CC list.

./scripts/checkpatch.pl --strict <patch1> <patch2>

 ./scripts/get_maintainer.pl --noroles --norolestats --nogit-fallback
--nogit <patch1> <patch2>

git send-email --suppress-cc all --dry-run --annotate --to
heiko@sntech.de --cc <..> <patch1> <patch2>

This SoC has no support in mainline linux kernel yet.
In all the following yaml documents for rk3568 we need headers with
defines for clocks and power domains, etc.

For example:
#include <dt-bindings/clock/rk3568-cru.h>
#include <dt-bindings/power/rk3568-power.h>

Could Rockchip submit first clocks and power drivers entries and a basic
rk3568.dtsi + evb dts?
Include a patch to this serie with 3 pcie nodes added to rk3568.dtsi.

A dtbs_check only works with a complete dtsi and evb dts.

make ARCH=arm64 dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml

On 1/18/21 10:17 AM, Simon Xue wrote:
> Signed-off-by: Simon Xue <xxm@rock-chips.com>
> ---
>  .../bindings/pci/rockchip-dw-pcie.yaml        | 101 ++++++++++++++++++
>  1 file changed, 101 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> new file mode 100644
> index 000000000000..fa664cfffb29
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> @@ -0,0 +1,101 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: DesignWare based PCIe RC controller on Rockchip SoCs
> +

> +maintainers:
> +  - Shawn Lin <shawn.lin@rock-chips.com>
> +  - Simon Xue <xxm@rock-chips.com>

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

Add only people with maintainer rights.


allOf:
  - $ref: /schemas/pci/pci-bus.yaml#

designware-pcie.txt is in need for conversion to yaml.
Include the things that are needed in this document for now.

> +
> +# We need a select here so we don't match all nodes with 'snps,dw-pcie'
> +select:
> +  properties:
> +    compatible:
> +      contains:
> +        const: rockchip,rk3568-pcie
> +  required:
> +    - compatible
> +
> +properties:
> +  compatible:

> +    enum:
> +      - rockchip,rk3568-pcie
> +      - snps,dw-pcie

    items:
      - const: rockchip,rk3568-pcie
      - const: snps,dw-pcie

> +
> +  reg:
> +    maxItems: 1

    interrupts:
      - description:
      - description:
      - description:
      - description:
      - description:

  interrupt-names:    items:
      - const: sys
      - const: pmc
      - const: msg
      - const: legacy
      - const: err

> +
> +  clocks:
> +    items:
> +      - description: AHB clock for PCIe master
> +      - description: AHB clock for PCIe slave
> +      - description: AHB clock for PCIe dbi
> +      - description: APB clock for PCIe
> +      - description: Auxiliary clock for PCIe
> +
> +  clock-names:
> +    items:
> +      - const: aclk_mst
> +      - const: aclk_slv
> +      - const: aclk_dbi
> +      - const: pclk
> +      - const: aux
> +


  msi-map: true

  power-domains:
    maxItems: 1

> +  resets:	maxItems: 1

> +    items:
> +      - description: PCIe pipe reset line

remove

> +
> +  reset-names:
	const: pipe

> +    items:
> +      - const: pipe

remove

> +
> +required:
> +  - compatible

> +  - "#address-cells"
> +  - "#size-cells"

already required in pci-bus.yaml

> +  - bus-range
> +  - reg
> +  - reg-names
> +  - clocks
> +  - clock-names

> +  - msi-map

not defined in pci-bus.yaml and designware-pcie.txt
add to document

> +  - num-lanes

> +  - phys
> +  - phy-names

not defined in pci-bus.yaml and designware-pcie.txt
add to document

   - power-domains

> +  - ranges

already required in pci-bus.yaml

> +  - resets
> +  - reset-names
> +

> +additionalProperties: false

unevaluatedProperties: false

If other documents are included use unevaluatedProperties.

> +
> +examples:
> +  - |

#include <dt-bindings/clock/rk3568-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/rk3568-power.h>

Missing defines


    bus {
        #address-cells = <2>;
        #size-cells = <2>;

dt-check uses standard 32 bit regs
this example is for 64 bit

> +    pcie3x2: pcie@fe280000 {
> +      compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";

> +      #address-cells = <3>;
> +      #size-cells = <2>;

sort things that start with # below

> +      bus-range = <0x20 0x2f>;

sort order is:
compatible
reg
interrupt
the rest in alphabetical order
things with #
no status in yaml examples


> +      reg = <0x3 0xc0800000 0x0 0x400000>,
> +            <0x0 0xfe280000 0x0 0x10000>;
> +      reg-names = "pcie-dbi", "pcie-apb";

		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "sys", "pmc", "msg", "legacy", "err";

> +      clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
> +               <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
> +               <&cru CLK_PCIE30X2_AUX_NDFT>;
> +      clock-names = "aclk_mst", "aclk_slv",
> +                    "aclk_dbi", "pclk",
> +                    "aux";
> +      msi-map = <0x2000 &its 0x2000 0x1000>;
> +      num-lanes = <2>;
> +      phys = <&pcie30phy>;
> +      phy-names = "pcie-phy";

    power-domains = <&power RK3568_PD_PIPE>;

> +      ranges = <0x00000800 0x0 0x80000000 0x3 0x80000000 0x0 0x800000
> +                0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000
> +                0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
> +      resets = <&cru SRST_PCIE30X2_POWERUP>;
> +      reset-names = "pipe";
> +    };

};

> +
> +...
> 

Make sure that all properties that show up in this node are checked!

	pcie2x1: pcie@fe260000 {
		compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xf>;
		clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
			 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
			 <&cru CLK_PCIE20_AUX_NDFT>;
		clock-names = "aclk_mst", "aclk_slv",
			      "aclk_dbi", "pclk", "aux";
		device_type = "pci";
		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
		linux,pci-domain = <0>;
		num-ib-windows = <6>;
		num-ob-windows = <2>;
		max-link-speed = <2>;
		msi-map = <0x0 &its 0x0 0x1000>;
		num-lanes = <1>;
		phys = <&combphy2_psq PHY_TYPE_PCIE>;
		phy-names = "pcie-phy";
		power-domains = <&power RK3568_PD_PIPE>;
		ranges = <0x00000800 0x0 0x00000000 0x3 0x00000000 0x0 0x800000
			  0x81000000 0x0 0x00800000 0x3 0x00800000 0x0 0x100000
			  0x83000000 0x0 0x00900000 0x3 0x00900000 0x0 0x3f700000>;
		reg = <0x3 0xc0000000 0x0 0x400000>,
		      <0x0 0xfe260000 0x0 0x10000>;
		reg-names = "pcie-dbi", "pcie-apb";
		resets = <&cru SRST_PCIE20_POWERUP>;
		reset-names = "pipe";
		status = "disabled";
	};
Heiko Stuebner Jan. 19, 2021, 1:14 p.m. UTC | #2
Hi Johan,

Am Dienstag, 19. Januar 2021, 14:07:41 CET schrieb Johan Jonker:
> Hi Simon,
> 
> Thank you for this patch for rk3568 pcie.
> 
> Include the Rockchip device tree maintainer and all other people/lists
> to the CC list.
> 
> ./scripts/checkpatch.pl --strict <patch1> <patch2>
> 
>  ./scripts/get_maintainer.pl --noroles --norolestats --nogit-fallback
> --nogit <patch1> <patch2>
> 
> git send-email --suppress-cc all --dry-run --annotate --to
> heiko@sntech.de --cc <..> <patch1> <patch2>
> 
> This SoC has no support in mainline linux kernel yet.
> In all the following yaml documents for rk3568 we need headers with
> defines for clocks and power domains, etc.
> 
> For example:
> #include <dt-bindings/clock/rk3568-cru.h>
> #include <dt-bindings/power/rk3568-power.h>
> 
> Could Rockchip submit first clocks and power drivers entries and a basic
> rk3568.dtsi + evb dts?
> Include a patch to this serie with 3 pcie nodes added to rk3568.dtsi.
> 
> A dtbs_check only works with a complete dtsi and evb dts.
> 
> make ARCH=arm64 dtbs_check
> DT_SCHEMA_FILES=Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> 
> On 1/18/21 10:17 AM, Simon Xue wrote:
> > Signed-off-by: Simon Xue <xxm@rock-chips.com>
> > ---
> >  .../bindings/pci/rockchip-dw-pcie.yaml        | 101 ++++++++++++++++++
> >  1 file changed, 101 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> > new file mode 100644
> > index 000000000000..fa664cfffb29
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> > @@ -0,0 +1,101 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: DesignWare based PCIe RC controller on Rockchip SoCs
> > +
> 
> > +maintainers:
> > +  - Shawn Lin <shawn.lin@rock-chips.com>
> > +  - Simon Xue <xxm@rock-chips.com>
> 
> maintainers:
>   - Heiko Stuebner <heiko@sntech.de>
> 
> Add only people with maintainer rights.

I'd disagree on this ;-)

The maintainer for individual drivers should be the persons who are
actually know the hardware. We have individual Rockchip developers
taking care of other drivers as well already.

And normally scripts/get_maintainer.pl should already include me
due to the wildcard for things having "rockchip" in the name.


Heiko
Johan Jonker Jan. 19, 2021, 3:11 p.m. UTC | #3
Hi Simon, Heiko,

On 1/19/21 2:14 PM, Heiko Stübner wrote:
> Hi Johan,
> 
> Am Dienstag, 19. Januar 2021, 14:07:41 CET schrieb Johan Jonker:
>> Hi Simon,
>>
>> Thank you for this patch for rk3568 pcie.
>>
>> Include the Rockchip device tree maintainer and all other people/lists
>> to the CC list.
>>
>> ./scripts/checkpatch.pl --strict <patch1> <patch2>
>>
>>  ./scripts/get_maintainer.pl --noroles --norolestats --nogit-fallback
>> --nogit <patch1> <patch2>
>>
>> git send-email --suppress-cc all --dry-run --annotate --to
>> heiko@sntech.de --cc <..> <patch1> <patch2>
>>
>> This SoC has no support in mainline linux kernel yet.
>> In all the following yaml documents for rk3568 we need headers with
>> defines for clocks and power domains, etc.
>>
>> For example:
>> #include <dt-bindings/clock/rk3568-cru.h>
>> #include <dt-bindings/power/rk3568-power.h>
>>
>> Could Rockchip submit first clocks and power drivers entries and a basic
>> rk3568.dtsi + evb dts?
>> Include a patch to this serie with 3 pcie nodes added to rk3568.dtsi.
>>
>> A dtbs_check only works with a complete dtsi and evb dts.
>>
>> make ARCH=arm64 dtbs_check
>> DT_SCHEMA_FILES=Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
>>
>> On 1/18/21 10:17 AM, Simon Xue wrote:
>>> Signed-off-by: Simon Xue <xxm@rock-chips.com>
>>> ---
>>>  .../bindings/pci/rockchip-dw-pcie.yaml        | 101 ++++++++++++++++++
>>>  1 file changed, 101 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
>>> new file mode 100644
>>> index 000000000000..fa664cfffb29
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
>>> @@ -0,0 +1,101 @@
>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: DesignWare based PCIe RC controller on Rockchip SoCs
>>> +
>>
>>> +maintainers:
>>> +  - Shawn Lin <shawn.lin@rock-chips.com>
>>> +  - Simon Xue <xxm@rock-chips.com>
>>
>> maintainers:
>>   - Heiko Stuebner <heiko@sntech.de>
>>
>> Add only people with maintainer rights.
> 
> I'd disagree on this ;-)

All roads leads to Heiko... ;)

It takes long term commitment.
Year in, year out.
Keeping yourself up to date with the latest pcei development.
Communicate in English.
Be able to submit patches without errors... ;)
Review other peoples patches.
Respond in short time.
Bug fixing.

If that's what you really want, then you must include a patch to this
serie for MAINTAINERS.

Check patch with:

./scripts/parse-maintainers.pl --input=MAINTAINERS --output=MAINTAINERS
--order

Otherwise it's safe to include that person mentioned above.

> 
> The maintainer for individual drivers should be the persons who are
> actually know the hardware. We have individual Rockchip developers
> taking care of other drivers as well already.
> 
> And normally scripts/get_maintainer.pl should already include me
> due to the wildcard for things having "rockchip" in the name.
> 
> 
> Heiko
> 
> 
>
Robin Murphy Jan. 19, 2021, 6:40 p.m. UTC | #4
On 2021-01-19 15:11, Johan Jonker wrote:
> Hi Simon, Heiko,
> 
> On 1/19/21 2:14 PM, Heiko Stübner wrote:
>> Hi Johan,
>>
>> Am Dienstag, 19. Januar 2021, 14:07:41 CET schrieb Johan Jonker:
>>> Hi Simon,
>>>
>>> Thank you for this patch for rk3568 pcie.
>>>
>>> Include the Rockchip device tree maintainer and all other people/lists
>>> to the CC list.
>>>
>>> ./scripts/checkpatch.pl --strict <patch1> <patch2>
>>>
>>>   ./scripts/get_maintainer.pl --noroles --norolestats --nogit-fallback
>>> --nogit <patch1> <patch2>
>>>
>>> git send-email --suppress-cc all --dry-run --annotate --to
>>> heiko@sntech.de --cc <..> <patch1> <patch2>
>>>
>>> This SoC has no support in mainline linux kernel yet.
>>> In all the following yaml documents for rk3568 we need headers with
>>> defines for clocks and power domains, etc.
>>>
>>> For example:
>>> #include <dt-bindings/clock/rk3568-cru.h>
>>> #include <dt-bindings/power/rk3568-power.h>
>>>
>>> Could Rockchip submit first clocks and power drivers entries and a basic
>>> rk3568.dtsi + evb dts?
>>> Include a patch to this serie with 3 pcie nodes added to rk3568.dtsi.
>>>
>>> A dtbs_check only works with a complete dtsi and evb dts.
>>>
>>> make ARCH=arm64 dtbs_check
>>> DT_SCHEMA_FILES=Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
>>>
>>> On 1/18/21 10:17 AM, Simon Xue wrote:
>>>> Signed-off-by: Simon Xue <xxm@rock-chips.com>
>>>> ---
>>>>   .../bindings/pci/rockchip-dw-pcie.yaml        | 101 ++++++++++++++++++
>>>>   1 file changed, 101 insertions(+)
>>>>   create mode 100644 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
>>>> new file mode 100644
>>>> index 000000000000..fa664cfffb29
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
>>>> @@ -0,0 +1,101 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: DesignWare based PCIe RC controller on Rockchip SoCs
>>>> +
>>>
>>>> +maintainers:
>>>> +  - Shawn Lin <shawn.lin@rock-chips.com>
>>>> +  - Simon Xue <xxm@rock-chips.com>
>>>
>>> maintainers:
>>>    - Heiko Stuebner <heiko@sntech.de>
>>>
>>> Add only people with maintainer rights.
>>
>> I'd disagree on this ;-)
> 
> All roads leads to Heiko... ;)
> 
> It takes long term commitment.
> Year in, year out.
> Keeping yourself up to date with the latest pcei development.
> Communicate in English.
> Be able to submit patches without errors... ;)
> Review other peoples patches.
> Respond in short time.
> Bug fixing.

Crikey, it's only a DT binding... :/

> If that's what you really want, then you must include a patch to this
> serie for MAINTAINERS.

I think if Bjorn and Lorenzo want a specifically named sub-maintainer 
for the driver itself, we can let them say so rather than presume.

Robin.

> 
> Check patch with:
> 
> ./scripts/parse-maintainers.pl --input=MAINTAINERS --output=MAINTAINERS
> --order
> 
> Otherwise it's safe to include that person mentioned above.
> 
>>
>> The maintainer for individual drivers should be the persons who are
>> actually know the hardware. We have individual Rockchip developers
>> taking care of other drivers as well already.
>>
>> And normally scripts/get_maintainer.pl should already include me
>> due to the wildcard for things having "rockchip" in the name.
>>
>>
>> Heiko
>>
>>
>>
> 
> 
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>
Robin Murphy Jan. 19, 2021, 7:58 p.m. UTC | #5
On 2021-01-19 13:07, Johan Jonker wrote:
> Hi Simon,
> 
> Thank you for this patch for rk3568 pcie.
> 
> Include the Rockchip device tree maintainer and all other people/lists
> to the CC list.
> 
> ./scripts/checkpatch.pl --strict <patch1> <patch2>
> 
>   ./scripts/get_maintainer.pl --noroles --norolestats --nogit-fallback
> --nogit <patch1> <patch2>
> 
> git send-email --suppress-cc all --dry-run --annotate --to
> heiko@sntech.de --cc <..> <patch1> <patch2>
> 
> This SoC has no support in mainline linux kernel yet.
> In all the following yaml documents for rk3568 we need headers with
> defines for clocks and power domains, etc.
> 
> For example:
> #include <dt-bindings/clock/rk3568-cru.h>
> #include <dt-bindings/power/rk3568-power.h>
> 
> Could Rockchip submit first clocks and power drivers entries and a basic
> rk3568.dtsi + evb dts?
> Include a patch to this serie with 3 pcie nodes added to rk3568.dtsi.
> 
> A dtbs_check only works with a complete dtsi and evb dts.

This is a bizarrely circular argument - we can't have a binding without 
a DT to try validating against it? That's not how it usually works. We 
review and merge bindings first, then drivers that consume them and DTs 
that implement them.

Examples within a binding itself do not need to represent a whole SoC, 
in fact that would usually just make them unnecessarily complicated. 
They do need to compile correctly in the `make dt_binding_check` 
environment, but if anything it makes more sense to strip down and 
simplify the example to fit that environment than to pile in enough 
other crap to realistically model all the supporting components from a 
particular SoC. Not least because the more extra stuff has to be crammed 
in, the more it distracts from the fundamental purpose of demonstrating 
*that specific binding* in use. For instance, a "clocks" property can 
quite happily use arbitrary numeric specifiers targeting a dummy clock 
controller node; requiring that some device binding depend on a 
particular clock controller binding being upstreamed just so that 
SoC-specific identifiers can then be used in an example would be rather 
absurd.

Robin.

> make ARCH=arm64 dtbs_check
> DT_SCHEMA_FILES=Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> 
> On 1/18/21 10:17 AM, Simon Xue wrote:
>> Signed-off-by: Simon Xue <xxm@rock-chips.com>
>> ---
>>   .../bindings/pci/rockchip-dw-pcie.yaml        | 101 ++++++++++++++++++
>>   1 file changed, 101 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
>> new file mode 100644
>> index 000000000000..fa664cfffb29
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
>> @@ -0,0 +1,101 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: DesignWare based PCIe RC controller on Rockchip SoCs
>> +
> 
>> +maintainers:
>> +  - Shawn Lin <shawn.lin@rock-chips.com>
>> +  - Simon Xue <xxm@rock-chips.com>
> 
> maintainers:
>    - Heiko Stuebner <heiko@sntech.de>
> 
> Add only people with maintainer rights.
> 
> 
> allOf:
>    - $ref: /schemas/pci/pci-bus.yaml#
> 
> designware-pcie.txt is in need for conversion to yaml.
> Include the things that are needed in this document for now.
> 
>> +
>> +# We need a select here so we don't match all nodes with 'snps,dw-pcie'
>> +select:
>> +  properties:
>> +    compatible:
>> +      contains:
>> +        const: rockchip,rk3568-pcie
>> +  required:
>> +    - compatible
>> +
>> +properties:
>> +  compatible:
> 
>> +    enum:
>> +      - rockchip,rk3568-pcie
>> +      - snps,dw-pcie
> 
>      items:
>        - const: rockchip,rk3568-pcie
>        - const: snps,dw-pcie
> 
>> +
>> +  reg:
>> +    maxItems: 1
> 
>      interrupts:
>        - description:
>        - description:
>        - description:
>        - description:
>        - description:
> 
>    interrupt-names:    items:
>        - const: sys
>        - const: pmc
>        - const: msg
>        - const: legacy
>        - const: err
> 
>> +
>> +  clocks:
>> +    items:
>> +      - description: AHB clock for PCIe master
>> +      - description: AHB clock for PCIe slave
>> +      - description: AHB clock for PCIe dbi
>> +      - description: APB clock for PCIe
>> +      - description: Auxiliary clock for PCIe
>> +
>> +  clock-names:
>> +    items:
>> +      - const: aclk_mst
>> +      - const: aclk_slv
>> +      - const: aclk_dbi
>> +      - const: pclk
>> +      - const: aux
>> +
> 
> 
>    msi-map: true
> 
>    power-domains:
>      maxItems: 1
> 
>> +  resets:	maxItems: 1
> 
>> +    items:
>> +      - description: PCIe pipe reset line
> 
> remove
> 
>> +
>> +  reset-names:
> 	const: pipe
> 
>> +    items:
>> +      - const: pipe
> 
> remove
> 
>> +
>> +required:
>> +  - compatible
> 
>> +  - "#address-cells"
>> +  - "#size-cells"
> 
> already required in pci-bus.yaml
> 
>> +  - bus-range
>> +  - reg
>> +  - reg-names
>> +  - clocks
>> +  - clock-names
> 
>> +  - msi-map
> 
> not defined in pci-bus.yaml and designware-pcie.txt
> add to document
> 
>> +  - num-lanes
> 
>> +  - phys
>> +  - phy-names
> 
> not defined in pci-bus.yaml and designware-pcie.txt
> add to document
> 
>     - power-domains
> 
>> +  - ranges
> 
> already required in pci-bus.yaml
> 
>> +  - resets
>> +  - reset-names
>> +
> 
>> +additionalProperties: false
> 
> unevaluatedProperties: false
> 
> If other documents are included use unevaluatedProperties.
> 
>> +
>> +examples:
>> +  - |
> 
> #include <dt-bindings/clock/rk3568-cru.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/power/rk3568-power.h>
> 
> Missing defines
> 
> 
>      bus {
>          #address-cells = <2>;
>          #size-cells = <2>;
> 
> dt-check uses standard 32 bit regs
> this example is for 64 bit
> 
>> +    pcie3x2: pcie@fe280000 {
>> +      compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
> 
>> +      #address-cells = <3>;
>> +      #size-cells = <2>;
> 
> sort things that start with # below
> 
>> +      bus-range = <0x20 0x2f>;
> 
> sort order is:
> compatible
> reg
> interrupt
> the rest in alphabetical order
> things with #
> no status in yaml examples
> 
> 
>> +      reg = <0x3 0xc0800000 0x0 0x400000>,
>> +            <0x0 0xfe280000 0x0 0x10000>;
>> +      reg-names = "pcie-dbi", "pcie-apb";
> 
> 		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
> 			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
> 			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> 			     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
> 			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> 		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
> 
>> +      clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
>> +               <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
>> +               <&cru CLK_PCIE30X2_AUX_NDFT>;
>> +      clock-names = "aclk_mst", "aclk_slv",
>> +                    "aclk_dbi", "pclk",
>> +                    "aux";
>> +      msi-map = <0x2000 &its 0x2000 0x1000>;
>> +      num-lanes = <2>;
>> +      phys = <&pcie30phy>;
>> +      phy-names = "pcie-phy";
> 
>      power-domains = <&power RK3568_PD_PIPE>;
> 
>> +      ranges = <0x00000800 0x0 0x80000000 0x3 0x80000000 0x0 0x800000
>> +                0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000
>> +                0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
>> +      resets = <&cru SRST_PCIE30X2_POWERUP>;
>> +      reset-names = "pipe";
>> +    };
> 
> };
> 
>> +
>> +...
>>
> 
> Make sure that all properties that show up in this node are checked!
> 
> 	pcie2x1: pcie@fe260000 {
> 		compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
> 		#address-cells = <3>;
> 		#size-cells = <2>;
> 		bus-range = <0x0 0xf>;
> 		clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
> 			 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
> 			 <&cru CLK_PCIE20_AUX_NDFT>;
> 		clock-names = "aclk_mst", "aclk_slv",
> 			      "aclk_dbi", "pclk", "aux";
> 		device_type = "pci";
> 		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
> 			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
> 			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> 			     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
> 			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> 		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
> 		linux,pci-domain = <0>;
> 		num-ib-windows = <6>;
> 		num-ob-windows = <2>;
> 		max-link-speed = <2>;
> 		msi-map = <0x0 &its 0x0 0x1000>;
> 		num-lanes = <1>;
> 		phys = <&combphy2_psq PHY_TYPE_PCIE>;
> 		phy-names = "pcie-phy";
> 		power-domains = <&power RK3568_PD_PIPE>;
> 		ranges = <0x00000800 0x0 0x00000000 0x3 0x00000000 0x0 0x800000
> 			  0x81000000 0x0 0x00800000 0x3 0x00800000 0x0 0x100000
> 			  0x83000000 0x0 0x00900000 0x3 0x00900000 0x0 0x3f700000>;
> 		reg = <0x3 0xc0000000 0x0 0x400000>,
> 		      <0x0 0xfe260000 0x0 0x10000>;
> 		reg-names = "pcie-dbi", "pcie-apb";
> 		resets = <&cru SRST_PCIE20_POWERUP>;
> 		reset-names = "pipe";
> 		status = "disabled";
> 	};
> 
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>
Simon Xue Jan. 20, 2021, 10:06 a.m. UTC | #6
Hi Johan,

Thanks for your review, I try to fix what you point out and get some 
consultations from others, please help to have

a look at the patch V2

Simon Xue.

在 2021/1/19 21:07, Johan Jonker 写道:
> Hi Simon,
>
> Thank you for this patch for rk3568 pcie.
>
> Include the Rockchip device tree maintainer and all other people/lists
> to the CC list.
>
> ./scripts/checkpatch.pl --strict <patch1> <patch2>
>
>   ./scripts/get_maintainer.pl --noroles --norolestats --nogit-fallback
> --nogit <patch1> <patch2>
>
> git send-email --suppress-cc all --dry-run --annotate --to
> heiko@sntech.de --cc <..> <patch1> <patch2>
>
> This SoC has no support in mainline linux kernel yet.
> In all the following yaml documents for rk3568 we need headers with
> defines for clocks and power domains, etc.
>
> For example:
> #include <dt-bindings/clock/rk3568-cru.h>
> #include <dt-bindings/power/rk3568-power.h>
>
> Could Rockchip submit first clocks and power drivers entries and a basic
> rk3568.dtsi + evb dts?
> Include a patch to this serie with 3 pcie nodes added to rk3568.dtsi.
>
> A dtbs_check only works with a complete dtsi and evb dts.
>
> make ARCH=arm64 dtbs_check
> DT_SCHEMA_FILES=Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
>
> On 1/18/21 10:17 AM, Simon Xue wrote:
>> Signed-off-by: Simon Xue <xxm@rock-chips.com>
>> ---
>>   .../bindings/pci/rockchip-dw-pcie.yaml        | 101 ++++++++++++++++++
>>   1 file changed, 101 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
>> new file mode 100644
>> index 000000000000..fa664cfffb29
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
>> @@ -0,0 +1,101 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: DesignWare based PCIe RC controller on Rockchip SoCs
>> +
>> +maintainers:
>> +  - Shawn Lin <shawn.lin@rock-chips.com>
>> +  - Simon Xue <xxm@rock-chips.com>
> maintainers:
>    - Heiko Stuebner <heiko@sntech.de>
>
> Add only people with maintainer rights.
>
>
> allOf:
>    - $ref: /schemas/pci/pci-bus.yaml#
>
> designware-pcie.txt is in need for conversion to yaml.
> Include the things that are needed in this document for now.
>
>> +
>> +# We need a select here so we don't match all nodes with 'snps,dw-pcie'
>> +select:
>> +  properties:
>> +    compatible:
>> +      contains:
>> +        const: rockchip,rk3568-pcie
>> +  required:
>> +    - compatible
>> +
>> +properties:
>> +  compatible:
>> +    enum:
>> +      - rockchip,rk3568-pcie
>> +      - snps,dw-pcie
>      items:
>        - const: rockchip,rk3568-pcie
>        - const: snps,dw-pcie
>
>> +
>> +  reg:
>> +    maxItems: 1
>      interrupts:
>        - description:
>        - description:
>        - description:
>        - description:
>        - description:
>
>    interrupt-names:    items:
>        - const: sys
>        - const: pmc
>        - const: msg
>        - const: legacy
>        - const: err
>
>> +
>> +  clocks:
>> +    items:
>> +      - description: AHB clock for PCIe master
>> +      - description: AHB clock for PCIe slave
>> +      - description: AHB clock for PCIe dbi
>> +      - description: APB clock for PCIe
>> +      - description: Auxiliary clock for PCIe
>> +
>> +  clock-names:
>> +    items:
>> +      - const: aclk_mst
>> +      - const: aclk_slv
>> +      - const: aclk_dbi
>> +      - const: pclk
>> +      - const: aux
>> +
>
>    msi-map: true
>
>    power-domains:
>      maxItems: 1
>
>> +  resets:	maxItems: 1
>> +    items:
>> +      - description: PCIe pipe reset line
> remove
>
>> +
>> +  reset-names:
> 	const: pipe
>
>> +    items:
>> +      - const: pipe
> remove
>
>> +
>> +required:
>> +  - compatible
>> +  - "#address-cells"
>> +  - "#size-cells"
> already required in pci-bus.yaml
>
>> +  - bus-range
>> +  - reg
>> +  - reg-names
>> +  - clocks
>> +  - clock-names
>> +  - msi-map
> not defined in pci-bus.yaml and designware-pcie.txt
> add to document
>
>> +  - num-lanes
>> +  - phys
>> +  - phy-names
> not defined in pci-bus.yaml and designware-pcie.txt
> add to document
>
>     - power-domains
>
>> +  - ranges
> already required in pci-bus.yaml
>
>> +  - resets
>> +  - reset-names
>> +
>> +additionalProperties: false
> unevaluatedProperties: false
>
> If other documents are included use unevaluatedProperties.
>
>> +
>> +examples:
>> +  - |
> #include <dt-bindings/clock/rk3568-cru.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/power/rk3568-power.h>
>
> Missing defines
>
>
>      bus {
>          #address-cells = <2>;
>          #size-cells = <2>;
>
> dt-check uses standard 32 bit regs
> this example is for 64 bit
>
>> +    pcie3x2: pcie@fe280000 {
>> +      compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
>> +      #address-cells = <3>;
>> +      #size-cells = <2>;
> sort things that start with # below
>
>> +      bus-range = <0x20 0x2f>;
> sort order is:
> compatible
> reg
> interrupt
> the rest in alphabetical order
> things with #
> no status in yaml examples
>
>
>> +      reg = <0x3 0xc0800000 0x0 0x400000>,
>> +            <0x0 0xfe280000 0x0 0x10000>;
>> +      reg-names = "pcie-dbi", "pcie-apb";
> 		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
> 			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
> 			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> 			     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
> 			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> 		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
>
>> +      clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
>> +               <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
>> +               <&cru CLK_PCIE30X2_AUX_NDFT>;
>> +      clock-names = "aclk_mst", "aclk_slv",
>> +                    "aclk_dbi", "pclk",
>> +                    "aux";
>> +      msi-map = <0x2000 &its 0x2000 0x1000>;
>> +      num-lanes = <2>;
>> +      phys = <&pcie30phy>;
>> +      phy-names = "pcie-phy";
>      power-domains = <&power RK3568_PD_PIPE>;
>
>> +      ranges = <0x00000800 0x0 0x80000000 0x3 0x80000000 0x0 0x800000
>> +                0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000
>> +                0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
>> +      resets = <&cru SRST_PCIE30X2_POWERUP>;
>> +      reset-names = "pipe";
>> +    };
> };
>
>> +
>> +...
>>
> Make sure that all properties that show up in this node are checked!
>
> 	pcie2x1: pcie@fe260000 {
> 		compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
> 		#address-cells = <3>;
> 		#size-cells = <2>;
> 		bus-range = <0x0 0xf>;
> 		clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
> 			 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
> 			 <&cru CLK_PCIE20_AUX_NDFT>;
> 		clock-names = "aclk_mst", "aclk_slv",
> 			      "aclk_dbi", "pclk", "aux";
> 		device_type = "pci";
> 		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
> 			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
> 			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> 			     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
> 			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> 		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
> 		linux,pci-domain = <0>;
> 		num-ib-windows = <6>;
> 		num-ob-windows = <2>;
> 		max-link-speed = <2>;
> 		msi-map = <0x0 &its 0x0 0x1000>;
> 		num-lanes = <1>;
> 		phys = <&combphy2_psq PHY_TYPE_PCIE>;
> 		phy-names = "pcie-phy";
> 		power-domains = <&power RK3568_PD_PIPE>;
> 		ranges = <0x00000800 0x0 0x00000000 0x3 0x00000000 0x0 0x800000
> 			  0x81000000 0x0 0x00800000 0x3 0x00800000 0x0 0x100000
> 			  0x83000000 0x0 0x00900000 0x3 0x00900000 0x0 0x3f700000>;
> 		reg = <0x3 0xc0000000 0x0 0x400000>,
> 		      <0x0 0xfe260000 0x0 0x10000>;
> 		reg-names = "pcie-dbi", "pcie-apb";
> 		resets = <&cru SRST_PCIE20_POWERUP>;
> 		reset-names = "pipe";
> 		status = "disabled";
> 	};
>
>
>
Rob Herring Jan. 20, 2021, 2:16 p.m. UTC | #7
On Tue, Jan 19, 2021 at 12:40 PM Robin Murphy <robin.murphy@arm.com> wrote:
>
> On 2021-01-19 15:11, Johan Jonker wrote:
> > Hi Simon, Heiko,
> >
> > On 1/19/21 2:14 PM, Heiko Stübner wrote:
> >> Hi Johan,
> >>
> >> Am Dienstag, 19. Januar 2021, 14:07:41 CET schrieb Johan Jonker:
> >>> Hi Simon,
> >>>
> >>> Thank you for this patch for rk3568 pcie.
> >>>
> >>> Include the Rockchip device tree maintainer and all other people/lists
> >>> to the CC list.
> >>>
> >>> ./scripts/checkpatch.pl --strict <patch1> <patch2>
> >>>
> >>>   ./scripts/get_maintainer.pl --noroles --norolestats --nogit-fallback
> >>> --nogit <patch1> <patch2>
> >>>
> >>> git send-email --suppress-cc all --dry-run --annotate --to
> >>> heiko@sntech.de --cc <..> <patch1> <patch2>
> >>>
> >>> This SoC has no support in mainline linux kernel yet.
> >>> In all the following yaml documents for rk3568 we need headers with
> >>> defines for clocks and power domains, etc.
> >>>
> >>> For example:
> >>> #include <dt-bindings/clock/rk3568-cru.h>
> >>> #include <dt-bindings/power/rk3568-power.h>
> >>>
> >>> Could Rockchip submit first clocks and power drivers entries and a basic
> >>> rk3568.dtsi + evb dts?
> >>> Include a patch to this serie with 3 pcie nodes added to rk3568.dtsi.
> >>>
> >>> A dtbs_check only works with a complete dtsi and evb dts.
> >>>
> >>> make ARCH=arm64 dtbs_check
> >>> DT_SCHEMA_FILES=Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> >>>
> >>> On 1/18/21 10:17 AM, Simon Xue wrote:
> >>>> Signed-off-by: Simon Xue <xxm@rock-chips.com>
> >>>> ---
> >>>>   .../bindings/pci/rockchip-dw-pcie.yaml        | 101 ++++++++++++++++++
> >>>>   1 file changed, 101 insertions(+)
> >>>>   create mode 100644 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> >>>>
> >>>> diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> >>>> new file mode 100644
> >>>> index 000000000000..fa664cfffb29
> >>>> --- /dev/null
> >>>> +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> >>>> @@ -0,0 +1,101 @@
> >>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> >>>> +%YAML 1.2
> >>>> +---
> >>>> +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
> >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>>> +
> >>>> +title: DesignWare based PCIe RC controller on Rockchip SoCs
> >>>> +
> >>>
> >>>> +maintainers:
> >>>> +  - Shawn Lin <shawn.lin@rock-chips.com>
> >>>> +  - Simon Xue <xxm@rock-chips.com>
> >>>
> >>> maintainers:
> >>>    - Heiko Stuebner <heiko@sntech.de>
> >>>
> >>> Add only people with maintainer rights.
> >>
> >> I'd disagree on this ;-)
> >
> > All roads leads to Heiko... ;)
> >
> > It takes long term commitment.
> > Year in, year out.
> > Keeping yourself up to date with the latest pcei development.
> > Communicate in English.
> > Be able to submit patches without errors... ;)
> > Review other peoples patches.
> > Respond in short time.
> > Bug fixing.
>
> Crikey, it's only a DT binding... :/
>
> > If that's what you really want, then you must include a patch to this
> > serie for MAINTAINERS.
>
> I think if Bjorn and Lorenzo want a specifically named sub-maintainer
> for the driver itself, we can let them say so rather than presume.

For the binding it's my call. :)

This should be someone who cares and knows the h/w. IOW, if I want to
delete the binding, someone who will object.

Of course, I'd like that someone to have all the above qualities too.

Rob
Heiko Stuebner Jan. 20, 2021, 2:54 p.m. UTC | #8
Am Mittwoch, 20. Januar 2021, 15:16:25 CET schrieb Rob Herring:
> On Tue, Jan 19, 2021 at 12:40 PM Robin Murphy <robin.murphy@arm.com> wrote:
> >
> > On 2021-01-19 15:11, Johan Jonker wrote:
> > > Hi Simon, Heiko,
> > >
> > > On 1/19/21 2:14 PM, Heiko Stübner wrote:
> > >> Hi Johan,
> > >>
> > >> Am Dienstag, 19. Januar 2021, 14:07:41 CET schrieb Johan Jonker:
> > >>> Hi Simon,
> > >>>
> > >>> Thank you for this patch for rk3568 pcie.
> > >>>
> > >>> Include the Rockchip device tree maintainer and all other people/lists
> > >>> to the CC list.
> > >>>
> > >>> ./scripts/checkpatch.pl --strict <patch1> <patch2>
> > >>>
> > >>>   ./scripts/get_maintainer.pl --noroles --norolestats --nogit-fallback
> > >>> --nogit <patch1> <patch2>
> > >>>
> > >>> git send-email --suppress-cc all --dry-run --annotate --to
> > >>> heiko@sntech.de --cc <..> <patch1> <patch2>
> > >>>
> > >>> This SoC has no support in mainline linux kernel yet.
> > >>> In all the following yaml documents for rk3568 we need headers with
> > >>> defines for clocks and power domains, etc.
> > >>>
> > >>> For example:
> > >>> #include <dt-bindings/clock/rk3568-cru.h>
> > >>> #include <dt-bindings/power/rk3568-power.h>
> > >>>
> > >>> Could Rockchip submit first clocks and power drivers entries and a basic
> > >>> rk3568.dtsi + evb dts?
> > >>> Include a patch to this serie with 3 pcie nodes added to rk3568.dtsi.
> > >>>
> > >>> A dtbs_check only works with a complete dtsi and evb dts.
> > >>>
> > >>> make ARCH=arm64 dtbs_check
> > >>> DT_SCHEMA_FILES=Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> > >>>
> > >>> On 1/18/21 10:17 AM, Simon Xue wrote:
> > >>>> Signed-off-by: Simon Xue <xxm@rock-chips.com>
> > >>>> ---
> > >>>>   .../bindings/pci/rockchip-dw-pcie.yaml        | 101 ++++++++++++++++++
> > >>>>   1 file changed, 101 insertions(+)
> > >>>>   create mode 100644 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> > >>>>
> > >>>> diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> > >>>> new file mode 100644
> > >>>> index 000000000000..fa664cfffb29
> > >>>> --- /dev/null
> > >>>> +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> > >>>> @@ -0,0 +1,101 @@
> > >>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > >>>> +%YAML 1.2
> > >>>> +---
> > >>>> +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
> > >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > >>>> +
> > >>>> +title: DesignWare based PCIe RC controller on Rockchip SoCs
> > >>>> +
> > >>>
> > >>>> +maintainers:
> > >>>> +  - Shawn Lin <shawn.lin@rock-chips.com>
> > >>>> +  - Simon Xue <xxm@rock-chips.com>
> > >>>
> > >>> maintainers:
> > >>>    - Heiko Stuebner <heiko@sntech.de>
> > >>>
> > >>> Add only people with maintainer rights.
> > >>
> > >> I'd disagree on this ;-)
> > >
> > > All roads leads to Heiko... ;)
> > >
> > > It takes long term commitment.
> > > Year in, year out.
> > > Keeping yourself up to date with the latest pcei development.
> > > Communicate in English.
> > > Be able to submit patches without errors... ;)
> > > Review other peoples patches.
> > > Respond in short time.
> > > Bug fixing.
> >
> > Crikey, it's only a DT binding... :/
> >
> > > If that's what you really want, then you must include a patch to this
> > > serie for MAINTAINERS.
> >
> > I think if Bjorn and Lorenzo want a specifically named sub-maintainer
> > for the driver itself, we can let them say so rather than presume.
> 
> For the binding it's my call. :)
> 
> This should be someone who cares and knows the h/w. IOW, if I want to
> delete the binding, someone who will object.
>
> Of course, I'd like that someone to have all the above qualities too.

I guess that would be separate entites then ...

Shawn and Simon know the hardware way better, though I'm not sure if their
work commitments will allow them to keep track of binding deletions

So maybe all 3 of us ;-)

Heiko
Robin Murphy Jan. 20, 2021, 4:20 p.m. UTC | #9
On 2021-01-20 14:54, Heiko Stübner wrote:
> Am Mittwoch, 20. Januar 2021, 15:16:25 CET schrieb Rob Herring:
>> On Tue, Jan 19, 2021 at 12:40 PM Robin Murphy <robin.murphy@arm.com> wrote:
>>>
>>> On 2021-01-19 15:11, Johan Jonker wrote:
>>>> Hi Simon, Heiko,
>>>>
>>>> On 1/19/21 2:14 PM, Heiko Stübner wrote:
>>>>> Hi Johan,
>>>>>
>>>>> Am Dienstag, 19. Januar 2021, 14:07:41 CET schrieb Johan Jonker:
>>>>>> Hi Simon,
>>>>>>
>>>>>> Thank you for this patch for rk3568 pcie.
>>>>>>
>>>>>> Include the Rockchip device tree maintainer and all other people/lists
>>>>>> to the CC list.
>>>>>>
>>>>>> ./scripts/checkpatch.pl --strict <patch1> <patch2>
>>>>>>
>>>>>>    ./scripts/get_maintainer.pl --noroles --norolestats --nogit-fallback
>>>>>> --nogit <patch1> <patch2>
>>>>>>
>>>>>> git send-email --suppress-cc all --dry-run --annotate --to
>>>>>> heiko@sntech.de --cc <..> <patch1> <patch2>
>>>>>>
>>>>>> This SoC has no support in mainline linux kernel yet.
>>>>>> In all the following yaml documents for rk3568 we need headers with
>>>>>> defines for clocks and power domains, etc.
>>>>>>
>>>>>> For example:
>>>>>> #include <dt-bindings/clock/rk3568-cru.h>
>>>>>> #include <dt-bindings/power/rk3568-power.h>
>>>>>>
>>>>>> Could Rockchip submit first clocks and power drivers entries and a basic
>>>>>> rk3568.dtsi + evb dts?
>>>>>> Include a patch to this serie with 3 pcie nodes added to rk3568.dtsi.
>>>>>>
>>>>>> A dtbs_check only works with a complete dtsi and evb dts.
>>>>>>
>>>>>> make ARCH=arm64 dtbs_check
>>>>>> DT_SCHEMA_FILES=Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
>>>>>>
>>>>>> On 1/18/21 10:17 AM, Simon Xue wrote:
>>>>>>> Signed-off-by: Simon Xue <xxm@rock-chips.com>
>>>>>>> ---
>>>>>>>    .../bindings/pci/rockchip-dw-pcie.yaml        | 101 ++++++++++++++++++
>>>>>>>    1 file changed, 101 insertions(+)
>>>>>>>    create mode 100644 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
>>>>>>>
>>>>>>> diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
>>>>>>> new file mode 100644
>>>>>>> index 000000000000..fa664cfffb29
>>>>>>> --- /dev/null
>>>>>>> +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
>>>>>>> @@ -0,0 +1,101 @@
>>>>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>>>>>> +%YAML 1.2
>>>>>>> +---
>>>>>>> +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
>>>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>>>> +
>>>>>>> +title: DesignWare based PCIe RC controller on Rockchip SoCs
>>>>>>> +
>>>>>>
>>>>>>> +maintainers:
>>>>>>> +  - Shawn Lin <shawn.lin@rock-chips.com>
>>>>>>> +  - Simon Xue <xxm@rock-chips.com>
>>>>>>
>>>>>> maintainers:
>>>>>>     - Heiko Stuebner <heiko@sntech.de>
>>>>>>
>>>>>> Add only people with maintainer rights.
>>>>>
>>>>> I'd disagree on this ;-)
>>>>
>>>> All roads leads to Heiko... ;)
>>>>
>>>> It takes long term commitment.
>>>> Year in, year out.
>>>> Keeping yourself up to date with the latest pcei development.
>>>> Communicate in English.
>>>> Be able to submit patches without errors... ;)
>>>> Review other peoples patches.
>>>> Respond in short time.
>>>> Bug fixing.
>>>
>>> Crikey, it's only a DT binding... :/
>>>
>>>> If that's what you really want, then you must include a patch to this
>>>> serie for MAINTAINERS.
>>>
>>> I think if Bjorn and Lorenzo want a specifically named sub-maintainer
>>> for the driver itself, we can let them say so rather than presume.
>>
>> For the binding it's my call. :)
>>
>> This should be someone who cares and knows the h/w. IOW, if I want to
>> delete the binding, someone who will object.
>>
>> Of course, I'd like that someone to have all the above qualities too.
> 
> I guess that would be separate entites then ...

Yup, that's the point I was trying to clarify - binding maintainer and 
driver maintainer are technically distinct roles. Of course if someone 
is a driver maintainer then it's usual - and preferable - for them to 
maintain the relevant bindings as well, so MAINTAINERS entries for 
drivers typically also cover those for convenience and pre-schema 
historical reasons. However, someone can take responsibility for a 
binding without signing up to explicitly maintain a corresponding driver 
(I know I have), and in that case the schema makes the binding 
self-documenting already - we don't have MAINTAINERS entries that *only* 
cover bindings, other than the top-level one that says Rob's in charge 
overall :)

Robin.

> Shawn and Simon know the hardware way better, though I'm not sure if their
> work commitments will allow them to keep track of binding deletions
> 
> So maybe all 3 of us ;-)
> 
> Heiko
> 
>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
new file mode 100644
index 000000000000..fa664cfffb29
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
@@ -0,0 +1,101 @@ 
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: DesignWare based PCIe RC controller on Rockchip SoCs
+
+maintainers:
+  - Shawn Lin <shawn.lin@rock-chips.com>
+  - Simon Xue <xxm@rock-chips.com>
+
+# We need a select here so we don't match all nodes with 'snps,dw-pcie'
+select:
+  properties:
+    compatible:
+      contains:
+        const: rockchip,rk3568-pcie
+  required:
+    - compatible
+
+properties:
+  compatible:
+    enum:
+      - rockchip,rk3568-pcie
+      - snps,dw-pcie
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: AHB clock for PCIe master
+      - description: AHB clock for PCIe slave
+      - description: AHB clock for PCIe dbi
+      - description: APB clock for PCIe
+      - description: Auxiliary clock for PCIe
+
+  clock-names:
+    items:
+      - const: aclk_mst
+      - const: aclk_slv
+      - const: aclk_dbi
+      - const: pclk
+      - const: aux
+
+  resets:
+    items:
+      - description: PCIe pipe reset line
+
+  reset-names:
+    items:
+      - const: pipe
+
+required:
+  - compatible
+  - "#address-cells"
+  - "#size-cells"
+  - bus-range
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+  - msi-map
+  - num-lanes
+  - phys
+  - phy-names
+  - ranges
+  - resets
+  - reset-names
+
+additionalProperties: false
+
+examples:
+  - |
+    pcie3x2: pcie@fe280000 {
+      compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
+      #address-cells = <3>;
+      #size-cells = <2>;
+      bus-range = <0x20 0x2f>;
+      reg = <0x3 0xc0800000 0x0 0x400000>,
+            <0x0 0xfe280000 0x0 0x10000>;
+      reg-names = "pcie-dbi", "pcie-apb";
+      clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
+               <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
+               <&cru CLK_PCIE30X2_AUX_NDFT>;
+      clock-names = "aclk_mst", "aclk_slv",
+                    "aclk_dbi", "pclk",
+                    "aux";
+      msi-map = <0x2000 &its 0x2000 0x1000>;
+      num-lanes = <2>;
+      phys = <&pcie30phy>;
+      phy-names = "pcie-phy";
+      ranges = <0x00000800 0x0 0x80000000 0x3 0x80000000 0x0 0x800000
+                0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000
+                0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
+      resets = <&cru SRST_PCIE30X2_POWERUP>;
+      reset-names = "pipe";
+    };
+
+...