diff mbox series

arm64: dts: rockchip: fix ranges property format for rk3399 pcie node

Message ID 20210122171243.16138-1-jbx6244@gmail.com (mailing list archive)
State New
Headers show
Series arm64: dts: rockchip: fix ranges property format for rk3399 pcie node | expand

Commit Message

Johan Jonker Jan. 22, 2021, 5:12 p.m. UTC
A test with the command below gives for example this error:
/arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml: pcie@f8000000:
ranges: 'oneOf' conditional failed, one must be fixed:

The pcie ranges property is an array. The dt-check expects that
each array item is wrapped with angle brackets, so fix that ranges
property format for the rk3399 pcie node.

make ARCH=arm64 dtbs_check
DT_SCHEMA_FILES=~/.local/lib/python3.5/site-packages/dtschema/
schemas/pci/pci-bus.yaml

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Heiko Stübner Jan. 25, 2021, 11:56 p.m. UTC | #1
On Fri, 22 Jan 2021 18:12:43 +0100, Johan Jonker wrote:
> A test with the command below gives for example this error:
> /arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml: pcie@f8000000:
> ranges: 'oneOf' conditional failed, one must be fixed:
> 
> The pcie ranges property is an array. The dt-check expects that
> each array item is wrapped with angle brackets, so fix that ranges
> property format for the rk3399 pcie node.
> 
> [...]

Applied, thanks!

[1/1] arm64: dts: rockchip: fix ranges property format for rk3399 pcie node
      commit: 6b8cc4b3e4c6a968fca48c3ef6477db755a78a3f

Best regards,
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 15f8b212c..28459d194 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -259,8 +259,8 @@ 
 		       <&pcie_phy 2>, <&pcie_phy 3>;
 		phy-names = "pcie-phy-0", "pcie-phy-1",
 			    "pcie-phy-2", "pcie-phy-3";
-		ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
-			  0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
+		ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
+			 <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
 		resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
 			 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
 			 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,