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[76.183.134.35]) by smtp.gmail.com with ESMTPSA id j20sm4148311oot.29.2021.05.26.11.16.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 May 2021 11:16:49 -0700 (PDT) From: Chris Morgan To: linux-mtd@lists.infradead.org Cc: linux-rockchip@lists.infradead.org, andy.yan@rock-chips.com, yifeng.zhao@rock-chips.com, sugar.zhang@rock-chips.com, tudor.ambarus@microchip.com, michael@walle.cc, p.yadav@ti.com, heiko@sntech.de, robh+dt@kernel.org, vigneshr@ti.com, richard@nod.at, miquel.raynal@bootlin.com, Chris Morgan Subject: [PATCH 2/3] mtd: spi-nor: Bindings for Rockchip serial flash controller Date: Wed, 26 May 2021 13:16:35 -0500 Message-Id: <20210526181636.1130-3-macroalpha82@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210526181636.1130-1-macroalpha82@gmail.com> References: <20210526181636.1130-1-macroalpha82@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210526_111653_203496_0DA914B5 X-CRM114-Status: GOOD ( 13.21 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org From: Chris Morgan Add binding document for the Rockchip serial flash controller. Signed-off-by: Chris Morgan --- .../mtd/rockchip,serialflash-controller.yaml | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/rockchip,serialflash-controller.yaml diff --git a/Documentation/devicetree/bindings/mtd/rockchip,serialflash-controller.yaml b/Documentation/devicetree/bindings/mtd/rockchip,serialflash-controller.yaml new file mode 100644 index 000000000000..97ea89fde3fb --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/rockchip,serialflash-controller.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/rockchip,serialflash-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip SoCs Serial FLASH Controller (SFC) + +maintainers: + - Andy Yan + +properties: + compatible: + oneOf: + - const: rockchip,px30-sfc + - const: rockchip,rv1108-sfc + - items: + - const: rockchip,sfc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 2 + items: + - description: Module Clock + - description: Bus Clock + + clock-names: + minItems: 2 + items: + - const: sfc + - const: hsfc + + power-domains: + maxItems: 1 + + rockchip,sfc-no-dma: + - descrption: Boolean value for disabling DMA + +patternProperties: + "^spi-nor@[0-3]$": + type: object + properties: + reg: + minimum: 0 + maximum: 3 + + spi-max-frequency: + maxItems: 1 + - description: Maximum frequency for SPI Flash + + compatible: + oneOf: + - const: jedec,spi-nor + + spi-rx-bus-width: + maxItems: 1 + - description: RX Bus Width (1x, 2x, or 4x mode) + + + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + +sfc: spi@ff3a0000 { + compatible = "rockchip,px30-sfc","rockchip,sfc"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xff3a0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "sfc", "hsfc"; + pinctrl-names = "default"; + pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>; + power-domains = <&power PX30_PD_MMC_NAND>; + + nor_flash: spi-nor@0 { + reg = <0>; + compatible = "xtx,xt25f128b","jedec,spi-nor"; + spi-rx-bus-width = <2>; + spi-max-frequency = <108000000>; + }; +}; + +...