diff mbox series

[2/2] arm64: dts: rockchip: add VPU node for rk3568

Message ID 20210719225806.26680-1-ezequiel@collabora.com (mailing list archive)
State New
Headers show
Series [1/2] arm64: dts: rockchip: add GPU node for rk3568 | expand

Commit Message

Ezequiel Garcia July 19, 2021, 10:58 p.m. UTC
Rockchip SoCs RK3566 and RK3568 several hardware
CODEC accelerators. This commit adds the Hantro G1
compatible one, which Rockchip labels as VDPU2.

The variant matches the RK3328 one.

Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
---
 arch/arm64/boot/dts/rockchip/rk3568.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

Comments

Heiko Stübner July 20, 2021, 9:14 a.m. UTC | #1
Am Dienstag, 20. Juli 2021, 00:58:06 CEST schrieb Ezequiel Garcia:
> Rockchip SoCs RK3566 and RK3568 several hardware
> CODEC accelerators. This commit adds the Hantro G1
> compatible one, which Rockchip labels as VDPU2.
> 
> The variant matches the RK3328 one.
> 
> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
> ---
>  arch/arm64/boot/dts/rockchip/rk3568.dtsi | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> index 59844dfaeb86..d9214f520400 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -398,6 +398,28 @@ gpu: gpu@fde60000 {
>  		status = "disabled";
>  	};
>  
> +	vpu: video-codec@fdea0400 {
> +		compatible = "rockchip,rk3328-vpu";

Do we want a 

		compatible = "rockchip,rk3568-vpu", "rockchip,rk3328-vpu";

here?

> +		reg = <0x0 0xfdea0000 0x0 0x800>;
> +		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "vdpu";
> +		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
> +		clock-names = "aclk", "hclk";
> +		iommus = <&vdpu_mmu>;
> +		power-domains = <&power RK3568_PD_VPU>;
> +	};
> +
> +	vdpu_mmu: iommu@fdea0800 {
> +		compatible = "rockchip,rk3568-iommu";
> +		reg = <0x0 0xfdea0800 0x0 0x40>;
> +		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "vdpu_mmu";
> +		clock-names = "aclk", "iface";
> +		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
> +		power-domains = <&power RK3568_PD_VPU>;
> +		#iommu-cells = <0>;
> +	};
> +
>  	sdmmc2: mmc@fe000000 {
>  		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
>  		reg = <0x0 0xfe000000 0x0 0x4000>;
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 59844dfaeb86..d9214f520400 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -398,6 +398,28 @@  gpu: gpu@fde60000 {
 		status = "disabled";
 	};
 
+	vpu: video-codec@fdea0400 {
+		compatible = "rockchip,rk3328-vpu";
+		reg = <0x0 0xfdea0000 0x0 0x800>;
+		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "vdpu";
+		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+		clock-names = "aclk", "hclk";
+		iommus = <&vdpu_mmu>;
+		power-domains = <&power RK3568_PD_VPU>;
+	};
+
+	vdpu_mmu: iommu@fdea0800 {
+		compatible = "rockchip,rk3568-iommu";
+		reg = <0x0 0xfdea0800 0x0 0x40>;
+		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "vdpu_mmu";
+		clock-names = "aclk", "iface";
+		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+		power-domains = <&power RK3568_PD_VPU>;
+		#iommu-cells = <0>;
+	};
+
 	sdmmc2: mmc@fe000000 {
 		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
 		reg = <0x0 0xfe000000 0x0 0x4000>;