diff mbox series

[v2,2/8] clk: rockchip: fix clk-pll rk356x early pll init

Message ID 20210728180034.717953-3-pgwipeout@gmail.com (mailing list archive)
State New
Headers show
Series fixes and enablement for rk356x | expand

Commit Message

Peter Geis July 28, 2021, 6 p.m. UTC
The rk356x needs to reclock certain plls at boot. If the grf phandles
are not linked in the cru and pmucru nodes, it is unable to apply any
assigned-clock-rates at boot.

Fix this by removing the check for the grf for selecting the utilized

"The rk3568 reuses the pll_rk3328-type which in turn is a modified
pll_rk3036 and uses their ops. Which in turn means the pll shouldn't
access the GRF at all, as it uses the pll's own register to check the
locked state."

Suggested-by: Heiko Stuebner <heiko@sntech.de>
Fixes: c9c3c6eecc55 ("clk: rockchip: simplify GRF handling in pll
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
 drivers/clk/rockchip/clk-pll.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series


diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index fe937bcdb487..f7827b3b7fc1 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -940,7 +940,7 @@  struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
 	switch (pll_type) {
 	case pll_rk3036:
 	case pll_rk3328:
-		if (!pll->rate_table || IS_ERR(ctx->grf))
+		if (!pll->rate_table)
 			init.ops = &rockchip_rk3036_pll_clk_norate_ops;
 			init.ops = &rockchip_rk3036_pll_clk_ops;