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Wed, 28 Jul 2021 11:00:57 -0700 (PDT) From: Peter Geis To: Michael Turquette , Stephen Boyd , Heiko Stuebner Cc: Peter Geis , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/8] clk: rockchip: fix clk-pll rk356x early pll init Date: Wed, 28 Jul 2021 14:00:28 -0400 Message-Id: <20210728180034.717953-3-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210728180034.717953-1-pgwipeout@gmail.com> References: <20210728180034.717953-1-pgwipeout@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210728_110059_697870_8F08C509 X-CRM114-Status: GOOD ( 15.29 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The rk356x needs to reclock certain plls at boot. If the grf phandles are not linked in the cru and pmucru nodes, it is unable to apply any assigned-clock-rates at boot. Fix this by removing the check for the grf for selecting the utilized operations. "The rk3568 reuses the pll_rk3328-type which in turn is a modified pll_rk3036 and uses their ops. Which in turn means the pll shouldn't access the GRF at all, as it uses the pll's own register to check the locked state." Suggested-by: Heiko Stuebner Link: https://lore.kernel.org/linux-devicetree/20210728135534.703028-7-pgwipeout@gmail.com/ Fixes: c9c3c6eecc55 ("clk: rockchip: simplify GRF handling in pll clocks") Signed-off-by: Peter Geis --- drivers/clk/rockchip/clk-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index fe937bcdb487..f7827b3b7fc1 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -940,7 +940,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, switch (pll_type) { case pll_rk3036: case pll_rk3328: - if (!pll->rate_table || IS_ERR(ctx->grf)) + if (!pll->rate_table) init.ops = &rockchip_rk3036_pll_clk_norate_ops; else init.ops = &rockchip_rk3036_pll_clk_ops;