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bh=uzvU0TWDqoO4AhItKda+Ka4vpknel8tSLxFVqVBoaHc=; b=gcxEyYrt5zIklO3ZNFDhNTxjF1tFRJDgikWDw10InAVO5b4ku7oXUDsfVAjifwYK6M WUCqcwyIQeB+4v7kL1zD5cdhHW1Y9PxsoB+xXmYT17AYuI3+Rgwu9OO52889mAkIRCDQ PIYi57tm5EDK/srLDXNeOkdvFAUFKsK2EymPmvQYWgBQeTXqxfyh8SWR1gcRVFuOdRSL PaJoKL05XQiHOKcHuPu3ky/F5iPsvqh31ntco1YxRgtzhKMcpcxPmxYIz2+6kIrzHQ/D +UfyKuKB/3W7NzU94uKyaWe8Vw25wQc9nzS+9JFPliPs1uNliEpfPcf4Pgl/gXdwA0d/ KO4w== X-Gm-Message-State: AOAM531emoFMRJ5gzGC9yTq3JSaQnhlK5Z66LcyH9RdNcVTrC2vEyyYo g1NVodOTB1FW0rgsBdd54o43tA== X-Google-Smtp-Source: ABdhPJyDQMGH0+RxUGQtHUeCYv4lJd35HOoioyP4NMAPxkHx4TB4s0fz74029ULAwuaRpQEaZQyUDw== X-Received: by 2002:a63:584:: with SMTP id 126mr4916161pgf.165.1631124839684; Wed, 08 Sep 2021 11:13:59 -0700 (PDT) Received: from localhost ([2620:15c:202:201:7556:e88d:6fba:e1d0]) by smtp.gmail.com with UTF8SMTPSA id o3sm2709858pji.26.2021.09.08.11.13.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Sep 2021 11:13:58 -0700 (PDT) From: Brian Norris To: Heiko Stuebner , Michael Turquette , Stephen Boyd Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-clk@vger.kernel.org, Chen-Yu Tsai , Douglas Anderson , linux-kernel@vger.kernel.org, Brian Norris Subject: [PATCH v2 1/3] clk: rockchip: rk3399: make CPU clocks critical Date: Wed, 8 Sep 2021 11:13:38 -0700 Message-Id: <20210908111337.v2.1.I006bb36063555079b1a88f01d20e38d7e4705ae0@changeid> X-Mailer: git-send-email 2.33.0.153.gba50c8fa24-goog MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210908_111405_852779_03A110AF X-CRM114-Status: GOOD ( 14.45 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The CPU clocks don't currently have any owner (e.g., cpufreq-dt doesn't enable() them -- and even if it did, it's not early enough compared to other consumers -- nor does arch/arm64/kernel/smp.c), and instead are simply assumed to be "on" all the time. They are also parents of a few other clocks which haven't been previously exposed for other devices to consume. If we want to expose those clocks, then the common clock framework may eventually choose to disable their parents (including the CPU PLLs) -- which is no fun for anyone. Thus, mark the CPU clocks as critical, to prevent them from being disabled implicitly. Signed-off-by: Brian Norris Reviewed-by: Douglas Anderson Reviewed-by: Chen-Yu Tsai --- Changes in v2: - New, split from the patch that requires this change drivers/clk/rockchip/clk-rk3399.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 62a4f2543960..0ac9c72c4ee8 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -1514,7 +1514,10 @@ static const char *const rk3399_cru_critical_clocks[] __initconst = { "aclk_vio_noc", /* ddrc */ - "sclk_ddrc" + "sclk_ddrc", + + "armclkl", + "armclkb", }; static const char *const rk3399_pmucru_critical_clocks[] __initconst = { @@ -1549,9 +1552,6 @@ static void __init rk3399_clk_init(struct device_node *np) rockchip_clk_register_branches(ctx, rk3399_clk_branches, ARRAY_SIZE(rk3399_clk_branches)); - rockchip_clk_protect_critical(rk3399_cru_critical_clocks, - ARRAY_SIZE(rk3399_cru_critical_clocks)); - rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl", mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), &rk3399_cpuclkl_data, rk3399_cpuclkl_rates, @@ -1562,6 +1562,9 @@ static void __init rk3399_clk_init(struct device_node *np) &rk3399_cpuclkb_data, rk3399_cpuclkb_rates, ARRAY_SIZE(rk3399_cpuclkb_rates)); + rockchip_clk_protect_critical(rk3399_cru_critical_clocks, + ARRAY_SIZE(rk3399_cru_critical_clocks)); + rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0), ROCKCHIP_SOFTRST_HIWORD_MASK);