From patchwork Tue Dec 7 01:54:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12660795 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3AB07C433EF for ; Tue, 7 Dec 2021 01:56:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=aRYblI/TrVwkB9oRNjAEFod4Z0gUs3jyppD0rb+MiFU=; b=ky0rET8ujCB1N4 WFt52oJxNxQO930Js8eTx/G1iha1mWoUzLuRF1LhQGLtPeP1DVAbClevx4hCuhpEmmMbP7KfvXTdC jBYFcX4stqmljfTNm4oJbEsAhrL0JAzIodIFR0oKJ4rzZ/SrVHZ/CE27EqKNC7NrWIxBFAAfnStFw jJo/YWPTOC7whDhmTq8qMDQXMUSpSfteZQDhfZ/r+gF6ND8zl6fERQ5YrhdcS1XVwMIsf1syFI2/F xiWAQIymSf2YmPgWJ2aCecovWyf0KHTIuAXv0oL+sP12Ek7R/cry9Xd4/DJ2PR02uFhJ6po0M657B tB1hQ7XKDGOEvNbHM7nw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1muPie-006fFq-Dy; Tue, 07 Dec 2021 01:56:36 +0000 Received: from mail-il1-x133.google.com ([2607:f8b0:4864:20::133]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1muPhF-006eJf-93; Tue, 07 Dec 2021 01:55:11 +0000 Received: by mail-il1-x133.google.com with SMTP id j7so12141256ilk.13; Mon, 06 Dec 2021 17:55:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zA35Y58P12mhcmBAnqxZhkfn5G9++KfvTLXr1jNa/3g=; b=QnF5iRdjFtybl/juAE4py5FH0qqAmQC1e+eyjUrU1r/nfX5ul7NRtBg7DqMqDa9VqF r4npcpH+pMu7CVpapcdHvPDL/HdX2N6Rb3sIYC77oXsReWo5gsdIaCZoj59Zur0iepLm DO/lQfzHvkv3MtUIWNQjPkkgpopXraY6WRnP6M9b50Crv+0rcWtK/UiECIc/jL7KKhdu UL2O29phnvkw5vq9PCY7f0c1wwDaUPYZO8tzJBjiv6WdaEioRpXTdUh2nKr7JJ7RRumz UX6NewtsGzCMVbPZHlv6vkztNd3DDLCSI5R3A8KympwEb5fyH0JJWpTferMFkGxrzTZQ CFig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zA35Y58P12mhcmBAnqxZhkfn5G9++KfvTLXr1jNa/3g=; b=rAbXhHE1hnx9Pcu7JzwpZv8E56jFcC4zhKqZgXTMPVQ0zdoYCG3RMWnIiXled17r2p lMSO/5GTIZ3CwmKys8ovHEIahloPMjUDAETQFc8uxkKXqK/ejGgY17Mat+PM8+9Y5PyT tCi3XKLF3fXkvp0k4RIxzKI7rSSeAfs1lSLgia8f/fMHBJ6wzKemC+hMCK/CTFW8bxsq XXKmJ5NGErChJ80cs6xdsLtNnfgsC/npX+bT3n+jpzuxCnSkqBWIMnFCavuttAZZuwCN MinCRRkMFwVc5f/n8P44nfkodiH2yrAIE+nFBj5g527ApaG49h/HjxhiHP2ixSEa5RBI RUfQ== X-Gm-Message-State: AOAM533rCrY6DizQhvZDP4FnkGN/j/HcyOtLyDeZrByqY6opNeu+ZUFc bOa1CLHO7saDGss63+XQF90= X-Google-Smtp-Source: ABdhPJyJgbJOu3Le6EQ1Ce0WpfUDTLfZY9Ktti+vSs5yIVRyR/wNK5ZMnFGUjdvNV9APxEk3RBv6cw== X-Received: by 2002:a92:730c:: with SMTP id o12mr34677255ilc.116.1638842107785; Mon, 06 Dec 2021 17:55:07 -0800 (PST) Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:6db8:c9e4:6f6d:f38e]) by smtp.gmail.com with ESMTPSA id j21sm8623639ila.6.2021.12.06.17.55.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 17:55:07 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: cphealy@gmail.com, benjamin.gaignard@collabora.com, hverkuil@xs4all.nl, Lucas Stach , Adam Ford , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Greg Kroah-Hartman , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: [RFC V2 4/6] soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrl Date: Mon, 6 Dec 2021 19:54:43 -0600 Message-Id: <20211207015446.1250854-5-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211207015446.1250854-1-aford173@gmail.com> References: <20211207015446.1250854-1-aford173@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211206_175509_392215_1842C277 X-CRM114-Status: GOOD ( 16.95 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org From: Lucas Stach This adds the necessary bits to drive the VPU blk-ctrl on the i.MX8MQ, to avoid putting more of this functionality into the decoder driver. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c index 519b3651d1d9..a7c12e8fa89b 100644 --- a/drivers/soc/imx/imx8m-blk-ctrl.c +++ b/drivers/soc/imx/imx8m-blk-ctrl.c @@ -14,6 +14,7 @@ #include #include +#include #define BLK_SFT_RSTN 0x0 #define BLK_CLK_EN 0x4 @@ -498,6 +499,68 @@ static const struct imx8m_blk_ctrl_data imx8mm_disp_blk_ctl_dev_data = { .num_domains = ARRAY_SIZE(imx8mm_disp_blk_ctl_domain_data), }; +static int imx8mq_vpu_power_notifier(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, + power_nb); + + if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) + return NOTIFY_OK; + + /* + * The ADB in the VPUMIX domain has no separate reset and clock + * enable bits, but is ungated and reset together with the VPUs. The + * reset and clock enable inputs to the ADB is a logical OR of the + * VPU bits. In order to set the G2 fuse bits, the G2 clock must + * also be enabled. + */ + regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1)); + regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1)); + + if (action == GENPD_NOTIFY_ON) { + /* + * On power up we have no software backchannel to the GPC to + * wait for the ADB handshake to happen, so we just delay for a + * bit. On power down the GPC driver waits for the handshake. + */ + udelay(5); + + /* set "fuse" bits to enable the VPUs */ + regmap_set_bits(bc->regmap, 0x8, 0xffffffff); + regmap_set_bits(bc->regmap, 0xc, 0xffffffff); + regmap_set_bits(bc->regmap, 0x10, 0xffffffff); + } + + return NOTIFY_OK; +} + +static const struct imx8m_blk_ctrl_domain_data imx8mq_vpu_blk_ctl_domain_data[] = { + [IMX8MQ_VPUBLK_PD_G1] = { + .name = "vpublk-g1", + .clk_names = (const char *[]){ "g1", }, + .num_clks = 1, + .gpc_name = "g1", + .rst_mask = BIT(1), + .clk_mask = BIT(1), + }, + [IMX8MQ_VPUBLK_PD_G2] = { + .name = "vpublk-g2", + .clk_names = (const char *[]){ "g2", }, + .num_clks = 1, + .gpc_name = "g2", + .rst_mask = BIT(0), + .clk_mask = BIT(0), + }, +}; + +static const struct imx8m_blk_ctrl_data imx8mq_vpu_blk_ctl_dev_data = { + .max_reg = 0x14, + .power_notifier_fn = imx8mq_vpu_power_notifier, + .domains = imx8mq_vpu_blk_ctl_domain_data, + .num_domains = ARRAY_SIZE(imx8mq_vpu_blk_ctl_domain_data), +}; + static const struct of_device_id imx8m_blk_ctrl_of_match[] = { { .compatible = "fsl,imx8mm-vpu-blk-ctrl", @@ -505,7 +568,10 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = { }, { .compatible = "fsl,imx8mm-disp-blk-ctrl", .data = &imx8mm_disp_blk_ctl_dev_data - } ,{ + }, { + .compatible = "fsl,imx8mq-vpu-blk-ctrl", + .data = &imx8mq_vpu_blk_ctl_dev_data + }, { /* Sentinel */ } };