| Message ID | 20220124023125.414794-11-aford173@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | media: hantro: imx8mq/imx8mm: Let VPU decoders get controlled by vpu-blk-ctrl | expand |
Hi Adam, On Sun, Jan 23, 2022 at 08:31:24PM -0600, Adam Ford wrote: > There are two decoders on the i.MX8M Mini controlled by the > vpu-blk-ctrl. The G1 supports H264 and VP8 while the > G2 support HEVC and VP9. > > Signed-off-by: Adam Ford <aford173@gmail.com> > Looks good. Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Thanks, Ezequiel > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > index 0c7a72c51a31..98aec4421713 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -1272,6 +1272,22 @@ gpu_2d: gpu@38008000 { > power-domains = <&pgc_gpu>; > }; > > + vpu_g1: video-codec@38300000 { > + compatible = "nxp,imx8mm-vpu-g1"; > + reg = <0x38300000 0x10000>; > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; > + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>; > + }; > + > + vpu_g2: video-codec@38310000 { > + compatible = "nxp,imx8mq-vpu-g2"; > + reg = <0x38310000 0x10000>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>; > + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>; > + }; > + > vpu_blk_ctrl: blk-ctrl@38330000 { > compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; > reg = <0x38330000 0x100>; > @@ -1282,6 +1298,12 @@ vpu_blk_ctrl: blk-ctrl@38330000 { > <&clk IMX8MM_CLK_VPU_G2_ROOT>, > <&clk IMX8MM_CLK_VPU_H1_ROOT>; > clock-names = "g1", "g2", "h1"; > + assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, > + <&clk IMX8MM_CLK_VPU_G2>; > + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, > + <&clk IMX8MM_VPU_PLL_OUT>; > + assigned-clock-rates = <600000000>, > + <600000000>; > #power-domain-cells = <1>; > }; > > -- > 2.32.0 >
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 0c7a72c51a31..98aec4421713 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1272,6 +1272,22 @@ gpu_2d: gpu@38008000 { power-domains = <&pgc_gpu>; }; + vpu_g1: video-codec@38300000 { + compatible = "nxp,imx8mm-vpu-g1"; + reg = <0x38300000 0x10000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>; + }; + + vpu_g2: video-codec@38310000 { + compatible = "nxp,imx8mq-vpu-g2"; + reg = <0x38310000 0x10000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>; + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>; + }; + vpu_blk_ctrl: blk-ctrl@38330000 { compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; reg = <0x38330000 0x100>; @@ -1282,6 +1298,12 @@ vpu_blk_ctrl: blk-ctrl@38330000 { <&clk IMX8MM_CLK_VPU_G2_ROOT>, <&clk IMX8MM_CLK_VPU_H1_ROOT>; clock-names = "g1", "g2", "h1"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, + <&clk IMX8MM_CLK_VPU_G2>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, + <&clk IMX8MM_VPU_PLL_OUT>; + assigned-clock-rates = <600000000>, + <600000000>; #power-domain-cells = <1>; };
There are two decoders on the i.MX8M Mini controlled by the vpu-blk-ctrl. The G1 supports H264 and VP8 while the G2 support HEVC and VP9. Signed-off-by: Adam Ford <aford173@gmail.com>