[v2] drm/bridge: synopsys/dw-hdmi: set cec clock rate

Commit Message

Peter Geis Jan. 26, 2022, 9:01 p.m. UTC

The hdmi-cec clock must be 32khz in order for cec to work correctly.
Ensure before enabling the clock we set it in order for the hardware to
work as expected.
Fixes hdmi-cec support on Rockchip devices.

Fixes: ebe32c3e282a ("drm/bridge: synopsys/dw-hdmi: Enable cec clock")

Signed-off-by: Peter Geis <[e-mail]>
---
Changelog:
v2:
- Set the clock rate before enabling the clock
---
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++
 1 file changed, 7 insertions(+)

Patch

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 54d8fdad395f..65c16455b76a 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -48,6 +48,9 @@ 
 
 #define HDMI14_MAX_TMDSCLK	340000000
 
+/* HDMI CEC needs a clock rate of 32khz */
+#define HDMI_CEC_CLK_RATE	32768
+
 enum hdmi_datamap {
 	RGB444_8B = 0x01,
 	RGB444_10B = 0x03,
@@ -3341,6 +3344,10 @@  struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
 		hdmi->cec_clk = NULL;
 		goto err_iahb;
 	} else {
+		ret = clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
+		if (ret)
+			dev_warn(hdmi->dev, "Cannot set HDMI cec clock rate: %d\n", ret);
+
 		ret = clk_prepare_enable(hdmi->cec_clk);
 		if (ret) {
 			dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n",