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[98.233.193.225]) by smtp.gmail.com with ESMTPSA id m4sm237427qkp.117.2022.01.26.13.01.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jan 2022 13:01:42 -0800 (PST) From: Peter Geis To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Archit Taneja , Pierre-Hugues Husson Cc: Peter Geis , Sascha Hauer , Robin Murphy , linux-rockchip@lists.infradead.org, =?utf-8?q?Heiko_St=C3=BCbner?= , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] drm/bridge: synopsys/dw-hdmi: set cec clock rate Date: Wed, 26 Jan 2022 16:01:37 -0500 Message-Id: <20220126210137.3065508-1-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220126_130144_745607_19EBB673 X-CRM114-Status: GOOD ( 10.57 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The hdmi-cec clock must be 32khz in order for cec to work correctly. Ensure before enabling the clock we set it in order for the hardware to work as expected. Fixes hdmi-cec support on Rockchip devices. Fixes: ebe32c3e282a ("drm/bridge: synopsys/dw-hdmi: Enable cec clock") Signed-off-by: Peter Geis --- Changelog: v2: - Set the clock rate before enabling the clock --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index 54d8fdad395f..65c16455b76a 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -48,6 +48,9 @@ #define HDMI14_MAX_TMDSCLK 340000000 +/* HDMI CEC needs a clock rate of 32khz */ +#define HDMI_CEC_CLK_RATE 32768 + enum hdmi_datamap { RGB444_8B = 0x01, RGB444_10B = 0x03, @@ -3341,6 +3344,10 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, hdmi->cec_clk = NULL; goto err_iahb; } else { + ret = clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE); + if (ret) + dev_warn(hdmi->dev, "Cannot set HDMI cec clock rate: %d\n", ret); + ret = clk_prepare_enable(hdmi->cec_clk); if (ret) { dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n",