From patchwork Thu Jan 27 23:07:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 12727493 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65029C43219 for ; Thu, 27 Jan 2022 23:08:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ePJ6AlxFK4jMQjE1QZQCpzoaL43XgfioKealkZnXGD4=; b=ndoAHUJarSjIQp 32ltDB8PTvIIBM6lGO2lv88AmGDpUYyZHBOn5ReIsMS8wP0Fku9ufqEpIzM2Pe+bIgQf16MhwbrJG oBsRhAJHx8Wv3zU5yOdNKam+m6D5GkZQzsdiS+QDN8XyKameaMrzLhqKxh2xkd7g+AF9ki6GBluNJ J9CzMRFMn0r6VYgQhltCnax1JOR+Ziyy/sPDfPdCVbdUD9nvQ7Zhr8AtDkKLFv6z5yR1ZU5qQ44zK JEyXfsN5e1IVgaR27Y+MnwzwEt/od2R4wJ8xYiJOZDF+4c9obSr7YISNRpYprOFsOsDE+wQ5AVcEG IkJaeOZO23TaeDDmmIRA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nDDsm-00HGUZ-Di; Thu, 27 Jan 2022 23:08:48 +0000 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nDDsT-00HGJL-QH for linux-rockchip@lists.infradead.org; Thu, 27 Jan 2022 23:08:32 +0000 Received: by mail-pj1-x102c.google.com with SMTP id my12-20020a17090b4c8c00b001b528ba1cd7so4757969pjb.1 for ; Thu, 27 Jan 2022 15:08:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ji/SQVVMeTn1tROVJbE5IrSuQIV7umlG4sAb9DJ1rd4=; b=GJM/8zOZW0jPtcOYOaNBWtQ+KSUyKvUuXiUYQWTAO1rDvzd7irsrnCeZWw+gY+dvAC H3rxT/8/ZAQ/SJDJWN7wVaxvIf4kTQZTn0JjyYXNgPVS470n10NfGh5KQRpfBL4P9EfB SdBUplDn/Oxn1fbUeU8O1CKRon/hgYYO7VUyQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ji/SQVVMeTn1tROVJbE5IrSuQIV7umlG4sAb9DJ1rd4=; b=mticQyxrVbTK38LKTBaZj0Yg3hMjYhjpjDsNxycmnvmr0+7ExfvknOl515F05FESXz FtioKnF0KEUInBPez3UD0frlUVusTumX8fiU7HAHg3T+3UbdfZ6qp4fVvTNLUnYKf4OH 9zRiG0bCPhptZmX/sYr0Ik8I4sArI0cUhwj601mJ272Wwa4Wcnb6QnFDrZ/FRe5jLdVO orSYSmCoWIQ6ftmBm2jEbq/Q9FVEs0UuD5z/wXDlLFaUJ0Vn7Gmx+35L/MpYZBitwflZ ipFizQjyo1Ia7D7/qgXI5T4fcQQ6fLQUAL3X9lWeoZsE+6HCpdaXgBHpFWzviovBDslu LfWQ== X-Gm-Message-State: AOAM5303lewoCMtygf+WmrXGoz6uGpAjMjL2CoEJSo8KOth9HZ2BkCUu urzzfnJqcJuyLKr5uyXvnkApaw== X-Google-Smtp-Source: ABdhPJx9wiK9xm45b/dDJyYOFbrCKmg/tP7sUb2cWXUt03ZZJppWUeBaQOtvpMF6ShLXjrrfnTWJFw== X-Received: by 2002:a17:902:c10c:: with SMTP id 12mr5903890pli.158.1643324908569; Thu, 27 Jan 2022 15:08:28 -0800 (PST) Received: from localhost ([2620:15c:202:201:723d:38a9:9e7f:3435]) by smtp.gmail.com with UTF8SMTPSA id f12sm517852pfj.37.2022.01.27.15.08.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Jan 2022 15:08:28 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Lin Huang , linux-arm-kernel@lists.infradead.org, Derek Basehore , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Heiko Stuebner , Brian Norris Subject: [PATCH v2 02/15] dt-bindings: devfreq: rk3399_dmc: Deprecate unused/redundant properties Date: Thu, 27 Jan 2022 15:07:13 -0800 Message-Id: <20220127150615.v2.2.I5ba582cd678d34c03d647e5500db8e33b7524d66@changeid> X-Mailer: git-send-email 2.35.0.rc0.227.g00780c9af4-goog In-Reply-To: <20220127230727.3369358-1-briannorris@chromium.org> References: <20220127230727.3369358-1-briannorris@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220127_150829_918613_78B23B58 X-CRM114-Status: GOOD ( 12.15 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org These DRAM configuration properties are all handled in ARM Trusted Firmware (and have been since the early days of this SoC), and there are no in-tree users of the DMC binding yet. It's better to just defer to firmware instead of maintaining this large list of properties. There's also some confusion about units: many of these are specified in MHz, but the downstream users and driver code are treating them as Hz, I believe. Rather than straighten all that out, I just drop them. Signed-off-by: Brian Norris --- (no changes since v1) .../bindings/devfreq/rk3399_dmc.yaml | 42 +++++++++---------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml index 467a7b5b374b..fd62a8cd62d5 100644 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml @@ -46,6 +46,7 @@ properties: finishes, a DCF interrupt is triggered. rockchip,ddr3_speed_bin: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the @@ -92,6 +93,7 @@ properties: if bus is idle for standby_idle * DFI clock cycles. rockchip,dram_dll_dis_freq: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: | Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less @@ -99,6 +101,7 @@ properties: Note: if DLL was bypassed, the odt will also stop working. rockchip,phy_dll_dis_freq: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: | Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency @@ -106,6 +109,7 @@ properties: Note: PHY DLL and PHY ODT are independent. rockchip,auto_pd_dis_freq: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: Defines the auto PD disable frequency in MHz. @@ -119,18 +123,21 @@ properties: disabled. rockchip,ddr3_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the DRAM side drive strength in ohms. Default value is 40. rockchip,ddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the DRAM side ODT strength in ohms. Default value is 120. rockchip,phy_ddr3_ca_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the phy side CA line @@ -138,12 +145,14 @@ properties: Default value is 40. rockchip,phy_ddr3_dq_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the PHY side DQ line (including DQS/DQ/DM line) drive strength. Default value is 40. rockchip,phy_ddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the PHY side ODT @@ -158,18 +167,21 @@ properties: disabled. rockchip,lpddr3_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the DRAM side drive strength in ohms. Default value is 34. rockchip,lpddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT strength in ohms. Default value is 240. rockchip,phy_lpddr3_ca_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the PHY side CA line @@ -177,12 +189,14 @@ properties: Default value is 40. rockchip,phy_lpddr3_dq_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line (including DQS/DQ/DM line) drive strength. Default value is 40. rockchip,phy_lpddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When dram type is LPDDR3, this parameter define the phy side odt @@ -197,42 +211,49 @@ properties: disabled. rockchip,lpddr4_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the DRAM side drive strength in ohms. Default value is 60. rockchip,lpddr4_dq_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on DQS/DQ line strength in ohms. Default value is 40. rockchip,lpddr4_ca_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on CA line strength in ohms. Default value is 40. rockchip,phy_lpddr4_ca_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side CA line (including command address line) drive strength. Default value is 40. rockchip,phy_lpddr4_ck_cs_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side clock line and CS line drive strength. Default value is 80. rockchip,phy_lpddr4_dq_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line (including DQS/DQ/DM line) drive strength. Default value is 80. rockchip,phy_lpddr4_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side ODT @@ -261,33 +282,12 @@ examples: clock-names = "dmc_clk"; operating-points-v2 = <&dmc_opp_table>; center-supply = <&ppvar_centerlogic>; - rockchip,ddr3_speed_bin = <21>; rockchip,pd_idle = <0x40>; rockchip,sr_idle = <0x2>; rockchip,sr_mc_gate_idle = <0x3>; rockchip,srpd_lite_idle = <0x4>; rockchip,standby_idle = <0x2000>; - rockchip,dram_dll_dis_freq = <300>; - rockchip,phy_dll_dis_freq = <125>; - rockchip,auto_pd_dis_freq = <666>; rockchip,ddr3_odt_dis_freq = <333>; - rockchip,ddr3_drv = <40>; - rockchip,ddr3_odt = <120>; - rockchip,phy_ddr3_ca_drv = <40>; - rockchip,phy_ddr3_dq_drv = <40>; - rockchip,phy_ddr3_odt = <240>; rockchip,lpddr3_odt_dis_freq = <333>; - rockchip,lpddr3_drv = <34>; - rockchip,lpddr3_odt = <240>; - rockchip,phy_lpddr3_ca_drv = <40>; - rockchip,phy_lpddr3_dq_drv = <40>; - rockchip,phy_lpddr3_odt = <240>; rockchip,lpddr4_odt_dis_freq = <333>; - rockchip,lpddr4_drv = <60>; - rockchip,lpddr4_dq_odt = <40>; - rockchip,lpddr4_ca_odt = <40>; - rockchip,phy_lpddr4_ca_drv = <40>; - rockchip,phy_lpddr4_ck_cs_drv = <80>; - rockchip,phy_lpddr4_dq_drv = <80>; - rockchip,phy_lpddr4_odt = <60>; };