| Message ID | 20220217082954.2967889-10-s.hauer@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/rockchip: RK356x VOP2 support | expand |
17.02.2022 11:29, Sascha Hauer пишет: > The rk3568 HDMI has an additional clock that needs to be enabled for the > HDMI controller to work. The purpose of that clock is not clear. It is > named "hclk" in the downstream driver, so use the same name. Have you checked that DSI works without the enabled hclk? I'd expect the whole VOP to be clock-gated.
On Thu, Feb 17, 2022 at 03:35:08PM +0300, Dmitry Osipenko wrote: > 17.02.2022 11:29, Sascha Hauer пишет: > > The rk3568 HDMI has an additional clock that needs to be enabled for the > > HDMI controller to work. The purpose of that clock is not clear. It is > > named "hclk" in the downstream driver, so use the same name. > > Have you checked that DSI works without the enabled hclk? I'd expect the > whole VOP to be clock-gated. No, I haven't checked that. I am not sure where you aiming at. The HCLK_VOP is supplied to the vop2 as well and the vop2 driver also enables this clock. Still, when the HDMI registers are accessed before the vop2 driver enables HCLK_VOP then the system hangs, so the HDMI needs it also. Sascha
17.02.2022 18:00, Sascha Hauer пишет: > On Thu, Feb 17, 2022 at 03:35:08PM +0300, Dmitry Osipenko wrote: >> 17.02.2022 11:29, Sascha Hauer пишет: >>> The rk3568 HDMI has an additional clock that needs to be enabled for the >>> HDMI controller to work. The purpose of that clock is not clear. It is >>> named "hclk" in the downstream driver, so use the same name. >> >> Have you checked that DSI works without the enabled hclk? I'd expect the >> whole VOP to be clock-gated. > > No, I haven't checked that. > > I am not sure where you aiming at. The HCLK_VOP is supplied to the vop2 > as well and the vop2 driver also enables this clock. Still, when the > HDMI registers are accessed before the vop2 driver enables HCLK_VOP then > the system hangs, so the HDMI needs it also. HDMI, MIPI and etc are a part of VOP. I'm curious whether MIPI should also hang, at least datasheet suggests that it should since hclk ungates the AHB part of the VOP's h/w module, which is used for registers access.
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 11acd4668ebef..45f66fd613a6d 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -76,6 +76,7 @@ struct rockchip_hdmi { const struct rockchip_hdmi_chip_data *chip_data; struct clk *ref_clk; struct clk *grf_clk; + struct clk *hclk_clk; struct dw_hdmi *hdmi; struct regulator *avdd_0v9; struct regulator *avdd_1v8; @@ -231,6 +232,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) return PTR_ERR(hdmi->grf_clk); } + hdmi->hclk_clk = devm_clk_get_optional(hdmi->dev, "hclk"); + if (PTR_ERR(hdmi->hclk_clk) == -EPROBE_DEFER) { + return -EPROBE_DEFER; + } else if (IS_ERR(hdmi->hclk_clk)) { + DRM_DEV_ERROR(hdmi->dev, "failed to get hclk_clk clock\n"); + return PTR_ERR(hdmi->hclk_clk); + } + hdmi->avdd_0v9 = devm_regulator_get(hdmi->dev, "avdd-0v9"); if (IS_ERR(hdmi->avdd_0v9)) return PTR_ERR(hdmi->avdd_0v9); @@ -598,6 +607,13 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, goto err_clk; } + ret = clk_prepare_enable(hdmi->hclk_clk); + if (ret) { + DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI hclk clock: %d\n", + ret); + goto err_clk; + } + if (hdmi->chip_data == &rk3568_chip_data) { regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1, HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |
The rk3568 HDMI has an additional clock that needs to be enabled for the HDMI controller to work. The purpose of that clock is not clear. It is named "hclk" in the downstream driver, so use the same name. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- Notes: Changes since v5: - Use devm_clk_get_optional rather than devm_clk_get drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)