diff mbox series

[v2] media: hantro: HEVC: unconditionnaly set pps_{cb/cr}_qp_offset values

Message ID 20220426135034.694655-1-benjamin.gaignard@collabora.com (mailing list archive)
State New
Headers show
Series [v2] media: hantro: HEVC: unconditionnaly set pps_{cb/cr}_qp_offset values | expand

Commit Message

Benjamin Gaignard April 26, 2022, 1:50 p.m. UTC
Always set pps_cb_qp_offset and pps_cr_qp_offset values in Hantro/G2
register whatever is V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT
flag value.
This fix CAINIT_G_SHARP_3 test in fluster.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
---
 drivers/staging/media/hantro/hantro_g2_hevc_dec.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

Comments

Sebastian Fricke April 26, 2022, 3:07 p.m. UTC | #1
Hey Benjamin,

On 26.04.2022 15:50, Benjamin Gaignard wrote:
>Always set pps_cb_qp_offset and pps_cr_qp_offset values in Hantro/G2
>register whatever is V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT
>flag value.
>This fix CAINIT_G_SHARP_3 test in fluster.

just a small typo:
s/fix/fixes the/

Greetings,
Sebastian
>
>Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
>---
> drivers/staging/media/hantro/hantro_g2_hevc_dec.c | 9 ++-------
> 1 file changed, 2 insertions(+), 7 deletions(-)
>
>diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
>index 6deb31b7b993..503f4b028bc5 100644
>--- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
>+++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
>@@ -194,13 +194,8 @@ static void set_params(struct hantro_ctx *ctx)
> 		hantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0);
> 	}
>
>-	if (pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT) {
>-		hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset);
>-		hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset);
>-	} else {
>-		hantro_reg_write(vpu, &g2_cb_qp_offset, 0);
>-		hantro_reg_write(vpu, &g2_cr_qp_offset, 0);
>-	}
>+	hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset);
>+	hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset);
>
> 	hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2);
> 	hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2);
>-- 
>2.32.0
>
Ezequiel Garcia May 3, 2022, 1:12 p.m. UTC | #2
Hi Benjamin,

On Tue, Apr 26, 2022 at 10:50 AM Benjamin Gaignard
<benjamin.gaignard@collabora.com> wrote:
>
> Always set pps_cb_qp_offset and pps_cr_qp_offset values in Hantro/G2
> register whatever is V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT
> flag value.

I would say we need more justification why this is correct, or at least
checking what the reference vendor implementation is doing (and mentioning
in the commit description so we can track it in the future).

> This fix CAINIT_G_SHARP_3 test in fluster.
>

This could sound like a tad a pedantic detail, but I'd say it's
important we stop refering to tests
as "fluster tests", and instead say something more correct as "HEVC
conformance test CAINIT_G_SHARP_3".

Also, when we are fixing conformance tests, let's please add the
Fluster score (in this case, I think it's
OK to refer to Fluster).

PS: Same comments apply to patch "media: hantro: HEVC: Fix reference
frames management".

Thanks,
Ezequiel

> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
> ---
>  drivers/staging/media/hantro/hantro_g2_hevc_dec.c | 9 ++-------
>  1 file changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
> index 6deb31b7b993..503f4b028bc5 100644
> --- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
> +++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
> @@ -194,13 +194,8 @@ static void set_params(struct hantro_ctx *ctx)
>                 hantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0);
>         }
>
> -       if (pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT) {
> -               hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset);
> -               hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset);
> -       } else {
> -               hantro_reg_write(vpu, &g2_cb_qp_offset, 0);
> -               hantro_reg_write(vpu, &g2_cr_qp_offset, 0);
> -       }
> +       hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset);
> +       hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset);
>
>         hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2);
>         hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2);
> --
> 2.32.0
>
Benjamin Gaignard May 3, 2022, 1:32 p.m. UTC | #3
Le 03/05/2022 à 15:12, Ezequiel Garcia a écrit :
> Hi Benjamin,
>
> On Tue, Apr 26, 2022 at 10:50 AM Benjamin Gaignard
> <benjamin.gaignard@collabora.com> wrote:
>> Always set pps_cb_qp_offset and pps_cr_qp_offset values in Hantro/G2
>> register whatever is V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT
>> flag value.
> I would say we need more justification why this is correct, or at least
> checking what the reference vendor implementation is doing (and mentioning
> in the commit description so we can track it in the future).

Yes that is what the vendor implementation is doing.

>
>> This fix CAINIT_G_SHARP_3 test in fluster.
>>
> This could sound like a tad a pedantic detail, but I'd say it's
> important we stop refering to tests
> as "fluster tests", and instead say something more correct as "HEVC
> conformance test CAINIT_G_SHARP_3".

As you want.

>
> Also, when we are fixing conformance tests, let's please add the
> Fluster score (in this case, I think it's
> OK to refer to Fluster).

We are fixing bugs in parallel in the driver, the uAPI and GStreamer
so fluster score evolution reflect that progression and maybe not only
what this patch is fixing.
The best I could says here is that patch fix HEVC conformance test
CAINIT_G_SHARP_3 so fluster score increase by one.

Regards,
Benjamin

>
> PS: Same comments apply to patch "media: hantro: HEVC: Fix reference
> frames management".
>
> Thanks,
> Ezequiel
>
>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
>> ---
>>   drivers/staging/media/hantro/hantro_g2_hevc_dec.c | 9 ++-------
>>   1 file changed, 2 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
>> index 6deb31b7b993..503f4b028bc5 100644
>> --- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
>> +++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
>> @@ -194,13 +194,8 @@ static void set_params(struct hantro_ctx *ctx)
>>                  hantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0);
>>          }
>>
>> -       if (pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT) {
>> -               hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset);
>> -               hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset);
>> -       } else {
>> -               hantro_reg_write(vpu, &g2_cb_qp_offset, 0);
>> -               hantro_reg_write(vpu, &g2_cr_qp_offset, 0);
>> -       }
>> +       hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset);
>> +       hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset);
>>
>>          hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2);
>>          hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2);
>> --
>> 2.32.0
>>
diff mbox series

Patch

diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
index 6deb31b7b993..503f4b028bc5 100644
--- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
+++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
@@ -194,13 +194,8 @@  static void set_params(struct hantro_ctx *ctx)
 		hantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0);
 	}
 
-	if (pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT) {
-		hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset);
-		hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset);
-	} else {
-		hantro_reg_write(vpu, &g2_cb_qp_offset, 0);
-		hantro_reg_write(vpu, &g2_cr_qp_offset, 0);
-	}
+	hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset);
+	hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset);
 
 	hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2);
 	hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2);