From patchwork Tue May 3 13:55:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 12835818 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AEF40C433F5 for ; Tue, 3 May 2022 13:55:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=b0MPLcpGIKVQB//B7ZRtxLSIZbwYwRKd5VhHJAWOs8A=; b=Ya/ooWdrNc8iKo FwR1wYWdoEfYGrXgP7QVY3bS83GoenMT7NouBxisGkYAHyhk+Z8bg5SHyakks1S0R5zRtHjvQwuqD zmzT8UxaLoOtDoFMZuLbXvhw5+JXvTy1Btk91bI3i4HyoT7T6IHxtXgG8cxeqCQk3AIPal+KKjE5z 0u+QTcLW4tTgMHhWzbN4/5kJ6IQqBzNPNMtWkvqTWqWqYWlvgk5m6IVJgOOTXkz22PFisc3Qm1kwZ q+ihhhjuXr+5MEM4ow53XTdDgYsK4UuEA1mX+HLWvp7ETY/BBMzZOWUL1RzNW40KvwbNQjVNbICbg Zcp7GPhad2J05VzyfeLw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nlt09-0067jr-8g; Tue, 03 May 2022 13:55:41 +0000 Received: from bhuna.collabora.co.uk ([46.235.227.227]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nlt06-0067iY-0l for linux-rockchip@lists.infradead.org; Tue, 03 May 2022 13:55:39 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: benjamin.gaignard) with ESMTPSA id 64CC91F429C0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1651586136; bh=P5xe8aK24FneKrejeJc2PeEEYU1RX6wkZjpKA6DtjL0=; h=From:To:Cc:Subject:Date:From; b=FctP2ezJ1BzuLidot3tZBewEQHmgjWSjKvaPpojBML/H6pY6ZFOht8x1DlUyHwuZ3 0TwHfMrqlr/17ABbP4t3eSdAl/1D0JQMhjx+AG9fO56ZLV0s969e8mHjspxxuN+adh Sx3OxcFS+Ngz4yVBUpNWpORWH05Az0NJ1CeTgJNhxqbI3wN6sQoByPKLBuQT/ycEUw tWCuAtEVcsV/2H39VBN3Cn6UzCm7WnKxY4wHbXwxQ3D/Qlf+wuS6FqUxDms7CFewXF VqnsI5YRV8UJax11e0wMqfR82z6C2EL1B+Q8S7W3ATSyyoIEEnNQrn20ftw7glliPy Qtib9O7YaoAYg== From: Benjamin Gaignard To: ezequiel@vanguardiasur.com.ar, p.zabel@pengutronix.de, mchehab@kernel.org, gregkh@linuxfoundation.org Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org, jon@nanocrew.net, aford173@gmail.com, kernel@collabora.com, Benjamin Gaignard Subject: [PATCH v3] media: hantro: HEVC: unconditionnaly set pps_{cb/cr}_qp_offset values Date: Tue, 3 May 2022 15:55:29 +0200 Message-Id: <20220503135529.683474-1-benjamin.gaignard@collabora.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220503_065538_233026_1842CCD3 X-CRM114-Status: UNSURE ( 8.34 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Always set pps_cb_qp_offset and pps_cr_qp_offset values in Hantro/G2 register whatever is V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT flag value. The vendor code does the case to set these values. This fix conformance test CAINIT_G_SHARP_3. Fluster HEVC score is increase by one with this patch. Signed-off-by: Benjamin Gaignard Reviewed-by: Ezequiel Garcia --- drivers/staging/media/hantro/hantro_g2_hevc_dec.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c index 6deb31b7b993..503f4b028bc5 100644 --- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c +++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c @@ -194,13 +194,8 @@ static void set_params(struct hantro_ctx *ctx) hantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0); } - if (pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT) { - hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset); - hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset); - } else { - hantro_reg_write(vpu, &g2_cb_qp_offset, 0); - hantro_reg_write(vpu, &g2_cr_qp_offset, 0); - } + hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset); + hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset); hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2); hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2);