From patchwork Thu Sep 15 16:39:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 12977627 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E576FC6FA8A for ; Thu, 15 Sep 2022 16:41:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IryF3Jke6oUSlpxk3rqD5xQZvBDQLJ8/2xsJMO4lJO4=; b=IdszA6LLd9ofhx Aois7EkOa9izYVgDClhTrYrOpMDHGi5JRwzQPH37HF7auo0H+FZG0WvjwlaYN3A/9RUc1QjY7H4zZ V9J7PbFQspgjWSCop9JgzLc7+rmrAZRx6G8tFBIvyj5ymHC6y+rJND/cJlfjz3qi4Tpfh8xyLF6q1 v/a6aiR/rlaBH0YL6641UU7/QsEAPW5ohu3swLoKtrTm7/RwaKuoHcfmq05Gy4omBrDEiFA2vx257 6MuPIIatURQXCJNILGR4A73IQOG4ZgtGU8a2cXoH9IySaQumuh9kK6JRk5eyplDJrvVZGjv62HEtG JVxIavKkWZqiry8a2ebQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oYrvf-00Dc1p-K7; Thu, 15 Sep 2022 16:41:31 +0000 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oYruc-00DbVo-Bp for linux-rockchip@lists.infradead.org; Thu, 15 Sep 2022 16:40:32 +0000 Received: by mail-pj1-x102b.google.com with SMTP id go6so14130644pjb.2 for ; Thu, 15 Sep 2022 09:40:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=edgeble-ai.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=yTHBMfD1NcCPUBh02/Ma/3rAPG950Pb3ZKFhg79D8RE=; b=DKICLsD6Je95zfVgCW7rSW0SNGx9rZlroYzHiVbCn7Ukb+xE2m8g0YpNAarBJyvNQ7 QjH1uzHXppE2V5BsFB6xoMlsORghTPILoZDspVPTwcUZOrQEyGh1z3E68SYddsEtLwC4 tKIgRABv7uMAk+pUxwUpQLeNUY0ql+ejZrZXC3EO8ODHBHSyhFYHIXMdME9GlAiw6LM2 bMc79MXPGZBQql2KVyAnyoxEYI5TaYNgIeyy15r9QHiPx/3eGf+CN4/eitSOX1DiUXoq uWlFKEjQe9gQXC54to/KIlOlOPSFWRSpyU/esXZf3AMZU+NgRl42mAIFWjzck5RqvFet kmew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=yTHBMfD1NcCPUBh02/Ma/3rAPG950Pb3ZKFhg79D8RE=; b=weqKWYbGiBMe8PQTlLWxlQX3ycsVq5FebukVxiRFt1L/byW3Q6zd1Ri2s6bT1O3r5d 2tb637RPVtWnHViC5ADu+KnYX4xQfdzIHAIMDqwSfLUEElq0feRY3QGcbxK11BUUX0ku 5pxjG+F0OmWyLDAVwEPTJUMcwD4BrAHdLKwHHX9dQNT9iDFnFjD87ZoR7sYyl2dJs1N1 53r1jMdVMC8pRucP+qemFDIRgtgDCruZZTrJv6/sNR3x+Pt2TXMON73DrRh7BnHd8FCb RYYod++iW0gjGVjZgnZ+BhxtIYAsY2A8C+qYbKh5o/+9BMirYEOt7aELEO2lHEGjcSrd 4Z2Q== X-Gm-Message-State: ACrzQf1N/prOx9i0kcaOTDAKgZ3StWRbzTJ3lk1gyAJPYB4CYqoeSROp JC0Fsgwsd9lcfI9vGx1gZt5oMg== X-Google-Smtp-Source: AMsMyM6Sv+NbvmNt+niEfviK4K+idV0MsNDWF8bI4PzDq0CY1KAsV9BuvlVRz0XR/edHU7on2N0KxQ== X-Received: by 2002:a17:902:ab8e:b0:174:11d5:b2ec with SMTP id f14-20020a170902ab8e00b0017411d5b2ecmr454752plr.18.1663260024984; Thu, 15 Sep 2022 09:40:24 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c00a:a073:f820:a732:fc7f:74df]) by smtp.gmail.com with ESMTPSA id x21-20020aa78f15000000b00540f3ac5fb8sm12841652pfr.69.2022.09.15.09.40.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Sep 2022 09:40:24 -0700 (PDT) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Kever Yang Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, Jagan Teki Subject: [PATCH v5 5/6] ARM: dts: rockchip: Add Rockchip RV1126 pinctrl Date: Thu, 15 Sep 2022 22:09:46 +0530 Message-Id: <20220915163947.1922183-6-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220915163947.1922183-1-jagan@edgeble.ai> References: <20220915163947.1922183-1-jagan@edgeble.ai> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220915_094026_438880_0F1ABD10 X-CRM114-Status: GOOD ( 17.15 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Add pinctrl definitions for Rockchip RV1126 and the pinctrl conf's are included it from arm64 rockchip devicetree path. Signed-off-by: Jagan Teki --- Changes for v5: - none Changes for v4: - update i2c pins - rebase on -next Changes for v3: - none Changes for v2: - spilt pinctrl as separate patch MAINTAINERS | 2 +- arch/arm/boot/dts/rv1126-pinctrl.dtsi | 212 ++++++++++++++++++++++++++ 2 files changed, 213 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/rv1126-pinctrl.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 9d7f64dc0efe..9ddb45285676 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2690,7 +2690,7 @@ F: Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml F: Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml F: Documentation/devicetree/bindings/spi/spi-rockchip.yaml F: arch/arm/boot/dts/rk3* -F: arch/arm/boot/dts/rv1108* +F: arch/arm/boot/dts/rv11* F: arch/arm/mach-rockchip/ F: drivers/*/*/*rockchip* F: drivers/*/*rockchip* diff --git a/arch/arm/boot/dts/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rv1126-pinctrl.dtsi new file mode 100644 index 000000000000..8d660d7c81ba --- /dev/null +++ b/arch/arm/boot/dts/rv1126-pinctrl.dtsi @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include +#include + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <1 RK_PA3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clko */ + <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>; + }; + }; + i2c0 { + /omit-if-no-ref/ + i2c0_xfer: i2c0-xfer { + rockchip,pins = + /* i2c0_scl */ + <0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>, + /* i2c0_sda */ + <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>; + }; + }; + sdmmc0 { + /omit-if-no-ref/ + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + /* sdmmc0_d0 */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + /* sdmmc0_clk */ + <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + /* sdmmc0_cmd */ + <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_det: sdmmc0-det { + rockchip,pins = + <0 RK_PA3 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc0_pwr: sdmmc0-pwr { + rockchip,pins = + <0 RK_PC0 1 &pcfg_pull_none>; + }; + }; + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_det: sdmmc1-det { + rockchip,pins = + <1 RK_PD0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc1_pwr: sdmmc1-pwr { + rockchip,pins = + <1 RK_PD1 2 &pcfg_pull_none>; + }; + }; + uart0 { + /omit-if-no-ref/ + uart0_xfer: uart0-xfer { + rockchip,pins = + /* uart0_rx */ + <1 RK_PC2 1 &pcfg_pull_up>, + /* uart0_tx */ + <1 RK_PC3 1 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + uart0_ctsn: uart0-ctsn { + rockchip,pins = + <1 RK_PC1 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart0_rtsn: uart0-rtsn { + rockchip,pins = + <1 RK_PC0 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart0_rtsn_gpio: uart0-rts-pin { + rockchip,pins = + <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rx_m0 */ + <0 RK_PB7 2 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <0 RK_PB6 2 &pcfg_pull_up>; + }; + }; + uart2 { + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rx_m1 */ + <3 RK_PA3 1 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <3 RK_PA2 1 &pcfg_pull_up>; + }; + }; + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rx_m0 */ + <3 RK_PC7 4 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <3 RK_PC6 4 &pcfg_pull_up>; + }; + }; + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rx_m0 */ + <3 RK_PA5 4 &pcfg_pull_up>, + /* uart4_tx_m0 */ + <3 RK_PA4 4 &pcfg_pull_up>; + }; + }; + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rx_m0 */ + <3 RK_PA7 4 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <3 RK_PA6 4 &pcfg_pull_up>; + }; + }; +};