| Message ID | 20220930102620.1568864-1-jay.xu@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | pinctrl/rockchip: re-fix RK3308 pinmux bits | expand |
Hello Jianqun Xu, On Fri, 30 Sep 2022 18:26:20 +0800 Jianqun Xu <jay.xu@rock-chips.com> wrote: > Part of pins from RK3308 SoCs have two registers to do pinmux, one is > the origin register with 2bits named by gpioxx_sel, and another with > 3bits and named by gpioxx_sel_plus. Are the "plus" registers documented anywhere? The reference manual I have does not mention them. > The default value is 2bits. But Rockchip downstream pinctrl driver has a > soc init for RK3308 to switch to the 3bits path. The first patch > upstream the support for RK3308 pinctrl but drop the soc init codes. > > The commit 1f3e25a06883 ("pinctrl: rockchip: fix RK3308 pinmux bits") try > to fix back to 2 bits path, but that will makes some iomux not be > supported. Sorry about that, of course I could not know because my documentation does not mention those registers. > @@ -3014,6 +3014,50 @@ static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) > static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, > rockchip_pinctrl_resume); > > + > +static int rk3308_soc_data_init(struct rockchip_pinctrl *info) > +{ > + int ret; > + > + #define RK3308_GRF_SOC_CON13 (0x608) > + #define RK3308_GRF_SOC_CON15 (0x610) > + > + /* RK3308_GRF_SOC_CON13 */ > + #define RK3308_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10)) > + #define RK3308_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) > + #define RK3308_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) > + > + /* RK3308_GRF_SOC_CON15 */ > + #define RK3308_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11)) > + #define RK3308_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) > + #define RK3308_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) > + > + /* > + * Enable the special ctrl of selected sources. > + * > + * Example reference to GRF_SOC_CON13 description: > + * > + * gpio2a2_sel_src_ctrl > + * IOMUX control source selection. > + * 1'b0: use basic GPIO2A_IOMUX[gpio2a2_sel] > + * 1'b1: use gpio2a2_sel_plus instead of GPIO2A_IOMUX[gpio2a2_sel] > + */ > + > + ret = regmap_write(info->regmap_base, RK3308_GRF_SOC_CON13, > + RK3308_GRF_I2C3_IOFUNC_SRC_CTRL | > + RK3308_GRF_GPIO2A3_SEL_SRC_CTRL | > + RK3308_GRF_GPIO2A2_SEL_SRC_CTRL); > + if (ret) > + return ret; > + > + ret = regmap_write(info->regmap_base, RK3308_GRF_SOC_CON15, > + RK3308_GRF_GPIO2C0_SEL_SRC_CTRL | > + RK3308_GRF_GPIO3B3_SEL_SRC_CTRL | > + RK3308_GRF_GPIO3B2_SEL_SRC_CTRL); > + > + return ret; > +} This is new code, not code that my patch has removed. Is it needed? How did the driver work before without this code? I think we need to clarify those registers before applying a fix that might create other problems. Best regards.
Hi Luca: BR -------------- jay.xu@rock-chips.com >Hello Jianqun Xu, > >On Fri, 30 Sep 2022 18:26:20 +0800 >Jianqun Xu <jay.xu@rock-chips.com> wrote: > >> Part of pins from RK3308 SoCs have two registers to do pinmux, one is >> the origin register with 2bits named by gpioxx_sel, and another with >> 3bits and named by gpioxx_sel_plus. > >Are the "plus" registers documented anywhere? At RK3308 TRM CH5 GRF, GRF_SOC_CON13 3 RW 0x0 gpio2a2_sel_src_ctrl IOMUX control source selection. 1'b0: use basic GPIO2A_IOMUX[gpio2a2_sel] 1'b1: use gpio2a2_sel_plus instead of GPIO2A_IOMUX[gpio2a2_sel] 2:0 RW 0x0 gpio2a2_sel_plus 3'b000: GPIO2_A2 3'b001: UART0_CTSN 3'b010: SPI0_CLK 3'b011: I2C2_SDA 3'b100: Reserved 3'b101: OWIRE_M2 Sorry I don't know about the trm you got from our company, if you cannot find this part, may require a new version ? > >The reference manual I have does not mention them. > >> The default value is 2bits. But Rockchip downstream pinctrl driver has a >> soc init for RK3308 to switch to the 3bits path. The first patch >> upstream the support for RK3308 pinctrl but drop the soc init codes. >> >> The commit 1f3e25a06883 ("pinctrl: rockchip: fix RK3308 pinmux bits") try >> to fix back to 2 bits path, but that will makes some iomux not be >> supported. > >Sorry about that, of course I could not know because my documentation >does not mention those registers. Never be mind, that is my mistask when I upstream the support fo rk3308. The upstream version will lack of function 4-7, but it works well for the function 0-3 Problem happens when I backport these patches to our driver and the uart work bad since our driver will set it to 3bits path. Anyway thanks for your patch and could help to do a verify and review for this patch ? > >> @@ -3014,6 +3014,50 @@ static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) >> static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, >> rockchip_pinctrl_resume); >> >> + >> +static int rk3308_soc_data_init(struct rockchip_pinctrl *info) >> +{ >> + int ret; >> + >> + #define RK3308_GRF_SOC_CON13 (0x608) >> + #define RK3308_GRF_SOC_CON15 (0x610) >> + >> + /* RK3308_GRF_SOC_CON13 */ >> + #define RK3308_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10)) >> + #define RK3308_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) >> + #define RK3308_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) >> + >> + /* RK3308_GRF_SOC_CON15 */ >> + #define RK3308_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11)) >> + #define RK3308_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) >> + #define RK3308_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) >> + >> + /* >> + * Enable the special ctrl of selected sources. >> + * >> + * Example reference to GRF_SOC_CON13 description: >> + * >> + * gpio2a2_sel_src_ctrl >> + * IOMUX control source selection. >> + * 1'b0: use basic GPIO2A_IOMUX[gpio2a2_sel] >> + * 1'b1: use gpio2a2_sel_plus instead of GPIO2A_IOMUX[gpio2a2_sel] >> + */ >> + >> + ret = regmap_write(info->regmap_base, RK3308_GRF_SOC_CON13, >> + RK3308_GRF_I2C3_IOFUNC_SRC_CTRL | >> + RK3308_GRF_GPIO2A3_SEL_SRC_CTRL | >> + RK3308_GRF_GPIO2A2_SEL_SRC_CTRL); >> + if (ret) >> + return ret; >> + >> + ret = regmap_write(info->regmap_base, RK3308_GRF_SOC_CON15, >> + RK3308_GRF_GPIO2C0_SEL_SRC_CTRL | >> + RK3308_GRF_GPIO3B3_SEL_SRC_CTRL | >> + RK3308_GRF_GPIO3B2_SEL_SRC_CTRL); >> + >> + return ret; >> +} > >This is new code, not code that my patch has removed. Is it needed? How >did the driver work before without this code? > I set these codes before pinctrl to register. the driver could work with 2bit or 3bit, but a problem is that if the uboot change it to 3bit, but the kernel not to do any set then it works bad, that what happend when I backport it. >I think we need to clarify those registers before applying a fix that >might create other problems. Reference uppper note, part of trm for gpio2_a2 > >Best regards. >-- >Luca Ceresoli, Bootlin >Embedded Linux and Kernel engineering >https://bootlin.com
Hello Jianqun, Il giorno Sat, 1 Oct 2022 08:42:25 +0800 "jay.xu@rock-chips.com" <jay.xu@rock-chips.com> ha scritto: > Hi Luca: > > BR > -------------- > jay.xu@rock-chips.com > >Hello Jianqun Xu, > > > >On Fri, 30 Sep 2022 18:26:20 +0800 > >Jianqun Xu <jay.xu@rock-chips.com> wrote: > > > >> Part of pins from RK3308 SoCs have two registers to do pinmux, one is > >> the origin register with 2bits named by gpioxx_sel, and another with > >> 3bits and named by gpioxx_sel_plus. > > > >Are the "plus" registers documented anywhere? > > At RK3308 TRM CH5 GRF, > > GRF_SOC_CON13 > > 3 RW 0x0 gpio2a2_sel_src_ctrl > IOMUX control source selection. > 1'b0: use basic GPIO2A_IOMUX[gpio2a2_sel] > 1'b1: use gpio2a2_sel_plus instead of GPIO2A_IOMUX[gpio2a2_sel] > > 2:0 RW 0x0 gpio2a2_sel_plus > 3'b000: GPIO2_A2 > 3'b001: UART0_CTSN > 3'b010: SPI0_CLK > 3'b011: I2C2_SDA > 3'b100: Reserved > 3'b101: OWIRE_M2 > > Sorry I don't know about the trm you got from our company, if you cannot find this part, > may require a new version ? First of all: is a complete TRM available for public download? I searched again, but didn't find any.
Hi Luca： -------------- jay.xu@rock-chips.com >Hello Jianqun, > >Il giorno Sat, 1 Oct 2022 08:42:25 +0800 >"jay.xu@rock-chips.com" <jay.xu@rock-chips.com> ha scritto: > >> Hi Luca: >> >> BR >> -------------- >> jay.xu@rock-chips.com >> >Hello Jianqun Xu, >> > >> >On Fri, 30 Sep 2022 18:26:20 +0800 >> >Jianqun Xu <jay.xu@rock-chips.com> wrote: >> > >> >> Part of pins from RK3308 SoCs have two registers to do pinmux, one is >> >> the origin register with 2bits named by gpioxx_sel, and another with >> >> 3bits and named by gpioxx_sel_plus. >> > >> >Are the "plus" registers documented anywhere? >> >> At RK3308 TRM CH5 GRF, >> >> GRF_SOC_CON13 >> >> 3 RW 0x0 gpio2a2_sel_src_ctrl >> IOMUX control source selection. >> 1'b0: use basic GPIO2A_IOMUX[gpio2a2_sel] >> 1'b1: use gpio2a2_sel_plus instead of GPIO2A_IOMUX[gpio2a2_sel] >> >> 2:0 RW 0x0 gpio2a2_sel_plus >> 3'b000: GPIO2_A2 >> 3'b001: UART0_CTSN >> 3'b010: SPI0_CLK >> 3'b011: I2C2_SDA >> 3'b100: Reserved >> 3'b101: OWIRE_M2 >> >> Sorry I don't know about the trm you got from our company, if you cannot find this part, >> may require a new version ? > >First of all: is a complete TRM available for public download? https://opensource.rock-chips.com/wiki_Main_Page @kever should add a trm for rk3308 ? > >I searched again, but didn't find any. > >-- >Luca Ceresoli, Bootlin >Embedded Linux and Kernel engineering >https://bootlin.com
Hello jay.xu, kever, On Sun, 2 Oct 2022 09:44:02 +0800 "jay.xu@rock-chips.com" <jay.xu@rock-chips.com> wrote: > Hi Luca： > > -------------- > jay.xu@rock-chips.com > >Hello Jianqun, > > > >Il giorno Sat, 1 Oct 2022 08:42:25 +0800 > >"jay.xu@rock-chips.com" <jay.xu@rock-chips.com> ha scritto: > > > >> Hi Luca: > >> > >> BR > >> -------------- > >> jay.xu@rock-chips.com > >> >Hello Jianqun Xu, > >> > > >> >On Fri, 30 Sep 2022 18:26:20 +0800 > >> >Jianqun Xu <jay.xu@rock-chips.com> wrote: > >> > > >> >> Part of pins from RK3308 SoCs have two registers to do pinmux, one is > >> >> the origin register with 2bits named by gpioxx_sel, and another with > >> >> 3bits and named by gpioxx_sel_plus. > >> > > >> >Are the "plus" registers documented anywhere? > >> > >> At RK3308 TRM CH5 GRF, > >> > >> GRF_SOC_CON13 > >> > >> 3 RW 0x0 gpio2a2_sel_src_ctrl > >> IOMUX control source selection. > >> 1'b0: use basic GPIO2A_IOMUX[gpio2a2_sel] > >> 1'b1: use gpio2a2_sel_plus instead of GPIO2A_IOMUX[gpio2a2_sel] > >> > >> 2:0 RW 0x0 gpio2a2_sel_plus > >> 3'b000: GPIO2_A2 > >> 3'b001: UART0_CTSN > >> 3'b010: SPI0_CLK > >> 3'b011: I2C2_SDA > >> 3'b100: Reserved > >> 3'b101: OWIRE_M2 > >> > >> Sorry I don't know about the trm you got from our company, if you cannot find this part, > >> may require a new version ? > > > >First of all: is a complete TRM available for public download? > > https://opensource.rock-chips.com/wiki_Main_Page > @kever should add a trm for rk3308 ? Indeed it would be great to have the documentation available in the above page! With that one would be able to understand the code, e.g. I would have understood on my own what register 0x608/0x610 is and I would not have sent my initial patch as is. So I subscribe to the proposal by Jay to have the complete TRM online!
Hello jay.xu, kever, On Mon, 10 Oct 2022 16:04:39 +0200 Luca Ceresoli <luca.ceresoli@bootlin.com> wrote: > Hello jay.xu, kever, > > On Sun, 2 Oct 2022 09:44:02 +0800 > "jay.xu@rock-chips.com" <jay.xu@rock-chips.com> wrote: > > > Hi Luca： > > > > -------------- > > jay.xu@rock-chips.com > > >Hello Jianqun, > > > > > >Il giorno Sat, 1 Oct 2022 08:42:25 +0800 > > >"jay.xu@rock-chips.com" <jay.xu@rock-chips.com> ha scritto: > > > > > >> Hi Luca: > > >> > > >> BR > > >> -------------- > > >> jay.xu@rock-chips.com > > >> >Hello Jianqun Xu, > > >> > > > >> >On Fri, 30 Sep 2022 18:26:20 +0800 > > >> >Jianqun Xu <jay.xu@rock-chips.com> wrote: > > >> > > > >> >> Part of pins from RK3308 SoCs have two registers to do pinmux, one is > > >> >> the origin register with 2bits named by gpioxx_sel, and another with > > >> >> 3bits and named by gpioxx_sel_plus. > > >> > > > >> >Are the "plus" registers documented anywhere? > > >> > > >> At RK3308 TRM CH5 GRF, > > >> > > >> GRF_SOC_CON13 > > >> > > >> 3 RW 0x0 gpio2a2_sel_src_ctrl > > >> IOMUX control source selection. > > >> 1'b0: use basic GPIO2A_IOMUX[gpio2a2_sel] > > >> 1'b1: use gpio2a2_sel_plus instead of GPIO2A_IOMUX[gpio2a2_sel] > > >> > > >> 2:0 RW 0x0 gpio2a2_sel_plus > > >> 3'b000: GPIO2_A2 > > >> 3'b001: UART0_CTSN > > >> 3'b010: SPI0_CLK > > >> 3'b011: I2C2_SDA > > >> 3'b100: Reserved > > >> 3'b101: OWIRE_M2 > > >> > > >> Sorry I don't know about the trm you got from our company, if you cannot find this part, > > >> may require a new version ? > > > > > >First of all: is a complete TRM available for public download? > > > > https://opensource.rock-chips.com/wiki_Main_Page > > @kever should add a trm for rk3308 ? > > Indeed it would be great to have the documentation available in the > above page! With that one would be able to understand the code, e.g. I > would have understood on my own what register 0x608/0x610 is and I > would not have sent my initial patch as is. > > So I subscribe to the proposal by Jay to have the complete TRM online! While I am still sure that public, complete documentation is the best for the benefit of Linux support, from the lack of feedback I suspect this is not coming soon. While we wait for it to happen, I think the best way to move forward is to at least add a complete list of the possible values for the "plus" registers in the kernel source code, either in the driver or in rk3308.dtsi. I consider this the very minimum needed. Without this, the next developer will also be unable to use SPI or some other feature, perhaps sending another patch to fix the same issue, breaking it again. Would you be OK with doing that? Best regards.
Hi Luca -------------- jay.xu@rock-chips.com >Hello jay.xu, kever, > >On Mon, 10 Oct 2022 16:04:39 +0200 >Luca Ceresoli <luca.ceresoli@bootlin.com> wrote: > >> Hello jay.xu, kever, >> >> On Sun, 2 Oct 2022 09:44:02 +0800 >> "jay.xu@rock-chips.com" <jay.xu@rock-chips.com> wrote: >> >> > Hi Luca： >> > >> > -------------- >> > jay.xu@rock-chips.com >> > >Hello Jianqun, >> > > >> > >Il giorno Sat, 1 Oct 2022 08:42:25 +0800 >> > >"jay.xu@rock-chips.com" <jay.xu@rock-chips.com> ha scritto: >> > > >> > >> Hi Luca: >> > >> >> > >> BR >> > >> -------------- >> > >> jay.xu@rock-chips.com >> > >> >Hello Jianqun Xu, >> > >> > >> > >> >On Fri, 30 Sep 2022 18:26:20 +0800 >> > >> >Jianqun Xu <jay.xu@rock-chips.com> wrote: >> > >> > >> > >> >> Part of pins from RK3308 SoCs have two registers to do pinmux, one is >> > >> >> the origin register with 2bits named by gpioxx_sel, and another with >> > >> >> 3bits and named by gpioxx_sel_plus. >> > >> > >> > >> >Are the "plus" registers documented anywhere? >> > >> >> > >> At RK3308 TRM CH5 GRF, >> > >> >> > >> GRF_SOC_CON13 >> > >> >> > >> 3 RW 0x0 gpio2a2_sel_src_ctrl >> > >> IOMUX control source selection. >> > >> 1'b0: use basic GPIO2A_IOMUX[gpio2a2_sel] >> > >> 1'b1: use gpio2a2_sel_plus instead of GPIO2A_IOMUX[gpio2a2_sel] >> > >> >> > >> 2:0 RW 0x0 gpio2a2_sel_plus >> > >> 3'b000: GPIO2_A2 >> > >> 3'b001: UART0_CTSN >> > >> 3'b010: SPI0_CLK >> > >> 3'b011: I2C2_SDA >> > >> 3'b100: Reserved >> > >> 3'b101: OWIRE_M2 >> > >> >> > >> Sorry I don't know about the trm you got from our company, if you cannot find this part, >> > >> may require a new version ? >> > > >> > >First of all: is a complete TRM available for public download? >> > >> > https://opensource.rock-chips.com/wiki_Main_Page >> > @kever should add a trm for rk3308 ? >> >> Indeed it would be great to have the documentation available in the >> above page! With that one would be able to understand the code, e.g. I >> would have understood on my own what register 0x608/0x610 is and I >> would not have sent my initial patch as is. >> >> So I subscribe to the proposal by Jay to have the complete TRM online! > >While I am still sure that public, complete documentation is the best >for the benefit of Linux support, from the lack of feedback I suspect >this is not coming soon. > >While we wait for it to happen, I think the best way to move forward is >to at least add a complete list of the possible values for the "plus" >registers in the kernel source code, either in the driver or in >rk3308.dtsi. I consider this the very minimum needed. Without this, the >next developer will also be unable to use SPI or some other feature, >perhaps sending another patch to fix the same issue, breaking it again. > >Would you be OK with doing that? okay, it depends on kever to update the trm or not, patch can be halt on currently > >Best regards. >-- >Luca Ceresoli, Bootlin >Embedded Linux and Kernel engineering >https://bootlin.com
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 32e41395fc76..293077450d10 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -535,35 +535,35 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { .bit = 8, .mask = 0xf }, { - /* gpio2a2_sel */ + /* gpio2a2_sel_plus */ .num = 2, .pin = 2, - .reg = 0x40, - .bit = 4, - .mask = 0x3 + .reg = 0x608, + .bit = 0, + .mask = 0x7 }, { - /* gpio2a3_sel */ + /* gpio2a3_sel_plus */ .num = 2, .pin = 3, - .reg = 0x40, - .bit = 6, - .mask = 0x3 + .reg = 0x608, + .bit = 4, + .mask = 0x7 }, { - /* gpio2c0_sel */ + /* gpio2c0_sel_plus */ .num = 2, .pin = 16, - .reg = 0x50, - .bit = 0, - .mask = 0x3 + .reg = 0x610, + .bit = 8, + .mask = 0x7 }, { - /* gpio3b2_sel */ + /* gpio3b2_sel_plus */ .num = 3, .pin = 10, - .reg = 0x68, - .bit = 4, - .mask = 0x3 + .reg = 0x610, + .bit = 0, + .mask = 0x7 }, { - /* gpio3b3_sel */ + /* gpio3b3_sel_plus */ .num = 3, .pin = 11, .reg = 0x68, @@ -3014,6 +3014,50 @@ static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, rockchip_pinctrl_resume); + +static int rk3308_soc_data_init(struct rockchip_pinctrl *info) +{ + int ret; + + #define RK3308_GRF_SOC_CON13 (0x608) + #define RK3308_GRF_SOC_CON15 (0x610) + + /* RK3308_GRF_SOC_CON13 */ + #define RK3308_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10)) + #define RK3308_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) + #define RK3308_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) + + /* RK3308_GRF_SOC_CON15 */ + #define RK3308_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11)) + #define RK3308_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) + #define RK3308_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) + + /* + * Enable the special ctrl of selected sources. + * + * Example reference to GRF_SOC_CON13 description: + * + * gpio2a2_sel_src_ctrl + * IOMUX control source selection. + * 1'b0: use basic GPIO2A_IOMUX[gpio2a2_sel] + * 1'b1: use gpio2a2_sel_plus instead of GPIO2A_IOMUX[gpio2a2_sel] + */ + + ret = regmap_write(info->regmap_base, RK3308_GRF_SOC_CON13, + RK3308_GRF_I2C3_IOFUNC_SRC_CTRL | + RK3308_GRF_GPIO2A3_SEL_SRC_CTRL | + RK3308_GRF_GPIO2A2_SEL_SRC_CTRL); + if (ret) + return ret; + + ret = regmap_write(info->regmap_base, RK3308_GRF_SOC_CON15, + RK3308_GRF_GPIO2C0_SEL_SRC_CTRL | + RK3308_GRF_GPIO3B3_SEL_SRC_CTRL | + RK3308_GRF_GPIO3B2_SEL_SRC_CTRL); + + return ret; +} + static int rockchip_pinctrl_probe(struct platform_device *pdev) { struct rockchip_pinctrl *info; @@ -3079,6 +3123,12 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) return PTR_ERR(info->regmap_pmu); } + if (ctrl->type == RK3308) { + ret = rk3308_soc_data_init(info); + if (ret) + return ret; + } + ret = rockchip_pinctrl_register(pdev, info); if (ret) return ret;
Part of pins from RK3308 SoCs have two registers to do pinmux, one is the origin register with 2bits named by gpioxx_sel, and another with 3bits and named by gpioxx_sel_plus. The default value is 2bits. But Rockchip downstream pinctrl driver has a soc init for RK3308 to switch to the 3bits path. The first patch upstream the support for RK3308 pinctrl but drop the soc init codes. The commit 1f3e25a06883 ("pinctrl: rockchip: fix RK3308 pinmux bits") try to fix back to 2 bits path, but that will makes some iomux not be supported. This patch re-fix the pinmux bits to 3bits path. Fixes: 1f3e25a06883 ("pinctrl: rockchip: fix RK3308 pinmux bits") Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> --- drivers/pinctrl/pinctrl-rockchip.c | 84 ++++++++++++++++++++++++------ 1 file changed, 67 insertions(+), 17 deletions(-)