diff mbox series

arm64: dts: rockchip: add rk3566 pcie2 node

Message ID 20221026172152.64513-1-f.kardame@manjaro.org (mailing list archive)
State New, archived
Headers show
Series arm64: dts: rockchip: add rk3566 pcie2 node | expand

Commit Message

Furkan Kardame Oct. 26, 2022, 5:21 p.m. UTC 
This patch adds nodes needed for pcie2
to work on rk3566-roc-pc

Signed-off-by: Furkan Kardame <f.kardame@manjaro.org>
---
 .../arm64/boot/dts/rockchip/rk3566-roc-pc.dts | 34 +++++++++++++++++++
 1 file changed, 34 insertions(+)

Comments

Heiko Stübner Oct. 30, 2022, 8:08 p.m. UTC | #1 
On Wed, 26 Oct 2022 20:21:53 +0300, Furkan Kardame wrote:
> This patch adds nodes needed for pcie2
> to work on rk3566-roc-pc
> 
> 

Applied, thanks!

[1/1] arm64: dts: rockchip: add rk3566 pcie2 node
      commit: 8ea13ce0800e3e3bf95da2424f87b649a6efecfa

I've adapted the patch subject to
    arm64: dts: rockchip: add pcie2 support for rk3566-roc-pc

Please make sure the patch subject matches the content
in future submissions :-) .

Best regards,
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
index dba648c2f..ab177c4f9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
@@ -82,6 +82,18 @@  vcc5v0_sys: vcc5v0-sys-regulator {
 		vin-supply = <&usb_5v>;
 	};
 
+	vcc3v3_pcie: vcc3v3-pcie-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_enable_h>;
+		regulator-name = "vcc3v3_pcie";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
 	vcc3v3_sys: vcc3v3-sys-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc3v3_sys";
@@ -122,6 +134,10 @@  &combphy1 {
 	status = "okay";
 };
 
+&combphy2 {
+	status = "okay";
+};
+
 &cpu0 {
 	cpu-supply = <&vdd_cpu>;
 };
@@ -447,6 +463,14 @@  rgmii_phy1: ethernet-phy@0 {
 	};
 };
 
+&pcie2x1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_reset_h>;
+	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
 &pinctrl {
 	bt {
 		bt_enable_h: bt-enable-h {
@@ -468,6 +492,16 @@  user_led_enable_h: user-led-enable-h {
 		};
 	};
 
+	pcie {
+		pcie_enable_h: pcie-enable-h {
+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie_reset_h: pcie-reset-h {
+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	pmic {
 		pmic_int: pmic_int {
 			rockchip,pins =