Message ID | 20221112114125.1637543-2-aholmes@omnom.net (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | arm64: dts: rockchip: rk356x: Fix PCIe register and range mappings | expand |
> The register and range mappings for the PCIe controller in Rockchip's > RK356x SoCs are incorrect. Replace them with corrected values from the > vendor BSP sources, updated to match current DT schema. Hi, Andrew This patch broken pcie3x2 on my board. And the wireless card on pcie2x1 is still not working. [ 0.405341] pcieport 0000:00:00.0: of_irq_parse_pci: failed with rc=-22 [ 0.670522] rockchip-dw-pcie 3c0800000.pcie: can't request region for resource [mem 0xf2000000-0xf2ffffff] [ 0.671527] rockchip-dw-pcie: probe of 3c0800000.pcie failed with error -16 [ 7.354521] pci 0000:00:00.0: of_irq_parse_pci: failed with rc=-22 [ 7.355116] mt7921e 0000:01:00.0: enabling device (0000 -> 0002) [ 7.355812] mt7921e: probe of 0000:01:00.0 failed with error -28 -- Thanks, Chukun
On Tue, Dec 06, 2022 at 12:23:22AM +0800, Chukun Pan wrote: > > The register and range mappings for the PCIe controller in Rockchip's > > RK356x SoCs are incorrect. Replace them with corrected values from the > > vendor BSP sources, updated to match current DT schema. > > Hi, Andrew > > This patch broken pcie3x2 on my board. That's because 32bit mapping for pcie3x2 config should start at 0xf0000000 and the patch declares it incorrectly at 0xf2000000. https://megous.com/dl/tmp/6d1a04195112b1e0.png > And the wireless card on pcie2x1 is still not working. > [ 0.405341] pcieport 0000:00:00.0: of_irq_parse_pci: failed with rc=-22 > [ 0.670522] rockchip-dw-pcie 3c0800000.pcie: can't request region for resource [mem 0xf2000000-0xf2ffffff] > [ 0.671527] rockchip-dw-pcie: probe of 3c0800000.pcie failed with error -16 > [ 7.354521] pci 0000:00:00.0: of_irq_parse_pci: failed with rc=-22 > [ 7.355116] mt7921e 0000:01:00.0: enabling device (0000 -> 0002) > [ 7.355812] mt7921e: probe of 0000:01:00.0 failed with error -28 That's ENOSPC. Who knows where it's comming from. Something for you to debug. ;) regards, o. > > -- > Thanks, > Chukun > > -- > 2.25.1 >
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index ba67b58f05b7..c1128d0c4406 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -94,9 +94,10 @@ pcie3x1: pcie@fe270000 { power-domains = <&power RK3568_PD_PIPE>; reg = <0x3 0xc0400000 0x0 0x00400000>, <0x0 0xfe270000 0x0 0x00010000>, - <0x3 0x7f000000 0x0 0x01000000>; - ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>, - <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>; + <0x0 0xf2000000 0x0 0x00100000>; + ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, + <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>, + <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>; reg-names = "dbi", "apb", "config"; resets = <&cru SRST_PCIE30X1_POWERUP>; reset-names = "pipe"; @@ -146,9 +147,10 @@ pcie3x2: pcie@fe280000 { power-domains = <&power RK3568_PD_PIPE>; reg = <0x3 0xc0800000 0x0 0x00400000>, <0x0 0xfe280000 0x0 0x00010000>, - <0x3 0xbf000000 0x0 0x01000000>; - ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>, - <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>; + <0x0 0xf2000000 0x0 0x01000000>; + ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, + <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>, + <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>; reg-names = "dbi", "apb", "config"; resets = <&cru SRST_PCIE30X2_POWERUP>; reset-names = "pipe"; diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 164708f1eb67..eec1d496c617 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -951,7 +951,7 @@ pcie2x1: pcie@fe260000 { compatible = "rockchip,rk3568-pcie"; reg = <0x3 0xc0000000 0x0 0x00400000>, <0x0 0xfe260000 0x0 0x00010000>, - <0x3 0x3f000000 0x0 0x01000000>; + <0x0 0xf4000000 0x0 0x00100000>; reg-names = "dbi", "apb", "config"; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, @@ -980,8 +980,9 @@ pcie2x1: pcie@fe260000 { phys = <&combphy2 PHY_TYPE_PCIE>; phy-names = "pcie-phy"; power-domains = <&power RK3568_PD_PIPE>; - ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000 - 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>; + ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, + <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, + <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; resets = <&cru SRST_PCIE20_POWERUP>; reset-names = "pipe"; #address-cells = <3>;