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([45.112.3.26]) by smtp.gmail.com with ESMTPSA id m3-20020a635803000000b0047681fa88d1sm1308587pgb.53.2022.12.23.05.26.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Dec 2022 05:26:03 -0800 (PST) From: Anand Moon To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski Cc: Anand Moon , Jagan Teki , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv1 linux-next 4/4] ARM: dts: rockchip: rv1126: Enable Ethernet for Neu2-IO Date: Fri, 23 Dec 2022 13:22:33 +0000 Message-Id: <20221223132235.16149-4-anand@edgeble.ai> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223132235.16149-1-anand@edgeble.ai> References: <20221223132235.16149-1-anand@edgeble.ai> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221223_052605_417897_564DCA3E X-CRM114-Status: UNSURE ( 8.65 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Rockchip RV1126 has GMAC 10/100/1000M ethernet controller. Enable ethernet node on Neu2-IO board. Signed-off-by: Anand Moon Signed-off-by: Jagan Teki --- arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts | 37 ++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts b/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts index dded0a12f0cd..bd592026eae6 100644 --- a/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts +++ b/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts @@ -22,6 +22,43 @@ chosen { }; }; +&gmac { + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>; + phy-mode = "rgmii"; + phy-handle = <&phy>; + assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, + <&cru CLK_GMAC_ETHERNET_OUT>; + assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>; + assigned-clock-rates = <125000000>, <0>, <25000000>; + phy-supply = <&vcc_3v3>; + tx_delay = <0x2a>; + rx_delay = <0x1a>; + status = "okay"; +}; + +&mdio { + phy: phy@0 { + compatible = "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <ð_phy_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + ethernet { + eth_phy_rst: eth-phy-rst { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed;