| Message ID | 20221227104837.27208-3-anand@edgeble.ai (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [PATCHv3,linux-next,1/4] dt-bindings: net: rockchip-dwmac: fix rv1126 compatible warning | expand |
On 12/27/22 11:48, Anand Moon wrote: > Rockchip RV1126 has GMAC 10/100/1000M ethernet controller > add GMAC node for RV1126 SoC. > > Signed-off-by: Anand Moon <anand@edgeble.ai> > Signed-off-by: Jagan Teki <jagan@edgeble.ai> > --- > v3: drop the gmac_clkin_m0 & gmac_clkin_m1 fix clock node which are not > used, Add SoB of Jagan Teki. > V2: drop SoB of Jagan Teki. > --- > arch/arm/boot/dts/rv1126.dtsi | 49 +++++++++++++++++++++++++++++++++++ > 1 file changed, 49 insertions(+) > > diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi > index 1cb43147e90b..e20fdd0d333c 100644 > --- a/arch/arm/boot/dts/rv1126.dtsi > +++ b/arch/arm/boot/dts/rv1126.dtsi > @@ -90,6 +90,55 @@ xin24m: oscillator { > #clock-cells = <0>; > }; > > + gmac: ethernet@ffc40000 { Nodes with a reg property are sort on reg address. Heiko can fix that.. ;) timer0: timer@ff660000 { gmac: ethernet@ffc40000 { emmc: mmc@ffc50000 { > + compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; > + reg = <0xffc40000 0x4000>; > + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "macirq", "eth_wake_irq"; > + rockchip,grf = <&grf>; > + clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, > + <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>, > + <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, > + <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>; > + clock-names = "stmmaceth", "mac_clk_rx", > + "mac_clk_tx", "clk_mac_ref", > + "aclk_mac", "pclk_mac", > + "clk_mac_speed", "ptp_ref"; > + resets = <&cru SRST_GMAC_A>; > + reset-names = "stmmaceth"; > + > + snps,mixed-burst; > + snps,tso; > + > + snps,axi-config = <&stmmac_axi_setup>; > + snps,mtl-rx-config = <&mtl_rx_setup>; > + snps,mtl-tx-config = <&mtl_tx_setup>; > + status = "disabled"; > + > + mdio: mdio { > + compatible = "snps,dwmac-mdio"; > + #address-cells = <0x1>; > + #size-cells = <0x0>; > + }; > + > + stmmac_axi_setup: stmmac-axi-config { > + snps,wr_osr_lmt = <4>; > + snps,rd_osr_lmt = <8>; > + snps,blen = <0 0 0 0 16 8 4>; > + }; > + > + mtl_rx_setup: rx-queues-config { > + snps,rx-queues-to-use = <1>; > + queue0 {}; > + }; > + > + mtl_tx_setup: tx-queues-config { > + snps,tx-queues-to-use = <1>; > + queue0 {}; > + }; > + }; > + > grf: syscon@fe000000 { > compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd"; > reg = <0xfe000000 0x20000>;
Hi Johan On Tue, 27 Dec 2022 at 17:25, Johan Jonker <jbx6244@gmail.com> wrote: > > > > On 12/27/22 11:48, Anand Moon wrote: > > Rockchip RV1126 has GMAC 10/100/1000M ethernet controller > > add GMAC node for RV1126 SoC. > > > > Signed-off-by: Anand Moon <anand@edgeble.ai> > > Signed-off-by: Jagan Teki <jagan@edgeble.ai> > > --- > > v3: drop the gmac_clkin_m0 & gmac_clkin_m1 fix clock node which are not > > used, Add SoB of Jagan Teki. > > V2: drop SoB of Jagan Teki. > > --- > > arch/arm/boot/dts/rv1126.dtsi | 49 +++++++++++++++++++++++++++++++++++ > > 1 file changed, 49 insertions(+) > > > > diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi > > index 1cb43147e90b..e20fdd0d333c 100644 > > --- a/arch/arm/boot/dts/rv1126.dtsi > > +++ b/arch/arm/boot/dts/rv1126.dtsi > > @@ -90,6 +90,55 @@ xin24m: oscillator { > > #clock-cells = <0>; > > }; > > > > > + gmac: ethernet@ffc40000 { > > Nodes with a reg property are sort on reg address. > Heiko can fix that.. ;) > > timer0: timer@ff660000 { > gmac: ethernet@ffc40000 { > emmc: mmc@ffc50000 { > will sort these on reg address. In the future. or the next version. Thanks. -Anand
diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi index 1cb43147e90b..e20fdd0d333c 100644 --- a/arch/arm/boot/dts/rv1126.dtsi +++ b/arch/arm/boot/dts/rv1126.dtsi @@ -90,6 +90,55 @@ xin24m: oscillator { #clock-cells = <0>; }; + gmac: ethernet@ffc40000 { + compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; + reg = <0xffc40000 0x4000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&grf>; + clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, + <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>, + <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, + <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "aclk_mac", "pclk_mac", + "clk_mac_speed", "ptp_ref"; + resets = <&cru SRST_GMAC_A>; + reset-names = "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + grf: syscon@fe000000 { compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd"; reg = <0xfe000000 0x20000>;