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([45.112.3.15]) by smtp.gmail.com with ESMTPSA id m2-20020a170902db0200b001930e89f5f6sm9301861plx.98.2023.01.10.22.48.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 22:48:59 -0800 (PST) From: Anand Moon To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski Cc: Johan Jonker , Anand Moon , Jagan Teki , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv4 linux-next 2/4] ARM: dts: rockchip: rv1126: Add ethernet rgmiim1 pin-control Date: Wed, 11 Jan 2023 06:48:37 +0000 Message-Id: <20230111064842.5322-2-anand@edgeble.ai> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111064842.5322-1-anand@edgeble.ai> References: <20230111064842.5322-1-anand@edgeble.ai> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230110_224900_002837_E8C466B5 X-CRM114-Status: GOOD ( 11.05 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Add ethernet pin-control for rv1126 SoC. Signed-off-by: Anand Moon Signed-off-by: Jagan Teki --- v4: drop Rev by Jagan: Both SoB and RoB of same person is incorrect. update the $subject. v3: add Rev by and SoB Jagan Teki. v2: drop SoB of Jagan Teki. --- arch/arm/boot/dts/rv1126-pinctrl.dtsi | 42 +++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rv1126-pinctrl.dtsi index 4bc419cc1210..b77021772781 100644 --- a/arch/arm/boot/dts/rv1126-pinctrl.dtsi +++ b/arch/arm/boot/dts/rv1126-pinctrl.dtsi @@ -11,6 +11,14 @@ * by adding changes at end of this file. */ &pinctrl { + clk_out_ethernet { + /omit-if-no-ref/ + clk_out_ethernetm1_pins: clk-out-ethernetm1-pins { + rockchip,pins = + /* clk_out_ethernet_m1 */ + <2 RK_PC5 2 &pcfg_pull_none>; + }; + }; emmc { /omit-if-no-ref/ emmc_rstnout: emmc-rstnout { @@ -61,6 +69,40 @@ i2c0_xfer: i2c0-xfer { <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>; }; }; + rgmii { + /omit-if-no-ref/ + rgmiim1_pins: rgmiim1-pins { + rockchip,pins = + /* rgmii_mdc_m1 */ + <2 RK_PC2 2 &pcfg_pull_none>, + /* rgmii_mdio_m1 */ + <2 RK_PC1 2 &pcfg_pull_none>, + /* rgmii_rxclk_m1 */ + <2 RK_PD3 2 &pcfg_pull_none>, + /* rgmii_rxd0_m1 */ + <2 RK_PB5 2 &pcfg_pull_none>, + /* rgmii_rxd1_m1 */ + <2 RK_PB6 2 &pcfg_pull_none>, + /* rgmii_rxd2_m1 */ + <2 RK_PC7 2 &pcfg_pull_none>, + /* rgmii_rxd3_m1 */ + <2 RK_PD0 2 &pcfg_pull_none>, + /* rgmii_rxdv_m1 */ + <2 RK_PB4 2 &pcfg_pull_none>, + /* rgmii_txclk_m1 */ + <2 RK_PD2 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txd0_m1 */ + <2 RK_PC3 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txd1_m1 */ + <2 RK_PC4 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txd2_m1 */ + <2 RK_PD1 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txd3_m1 */ + <2 RK_PA4 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txen_m1 */ + <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>; + }; + }; sdmmc0 { /omit-if-no-ref/ sdmmc0_bus4: sdmmc0-bus4 {