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([45.112.3.15]) by smtp.gmail.com with ESMTPSA id m2-20020a170902db0200b001930e89f5f6sm9301861plx.98.2023.01.10.22.49.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 22:49:05 -0800 (PST) From: Anand Moon To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Richard Cochran Cc: Johan Jonker , Anand Moon , Jagan Teki , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCHv4 linux-next 3/4] Rockchip RV1126 has GMAC 10/100/1000M ethernet controller Date: Wed, 11 Jan 2023 06:48:38 +0000 Message-Id: <20230111064842.5322-3-anand@edgeble.ai> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111064842.5322-1-anand@edgeble.ai> References: <20230111064842.5322-1-anand@edgeble.ai> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230110_224908_798334_B1CFB631 X-CRM114-Status: UNSURE ( 9.76 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Add Ethernet GMAC node for RV1126 SoC. Signed-off-by: Anand Moon Signed-off-by: Jagan Teki Signed-off-by: Jagan Teki Signed-off-by: Anand Moon --- v4: sort the node as reg adds. update the commit message. v3: drop the gmac_clkin_m0 & gmac_clkin_m1 fix clock node which are not used, Add SoB of Jagan Teki. v2: drop SoB of Jagan Teki. --- arch/arm/boot/dts/rv1126.dtsi | 49 +++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi index 1cb43147e90b..1f07d0a4fa73 100644 --- a/arch/arm/boot/dts/rv1126.dtsi +++ b/arch/arm/boot/dts/rv1126.dtsi @@ -332,6 +332,55 @@ timer0: timer@ff660000 { clock-names = "pclk", "timer"; }; + gmac: ethernet@ffc40000 { + compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; + reg = <0xffc40000 0x4000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&grf>; + clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, + <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>, + <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, + <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "aclk_mac", "pclk_mac", + "clk_mac_speed", "ptp_ref"; + resets = <&cru SRST_GMAC_A>; + reset-names = "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + emmc: mmc@ffc50000 { compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0xffc50000 0x4000>;