| Message ID | 20230113101604.261429-1-benjamin.gaignard@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | media: verisilicon: HEVC: Only propose 10 bits compatible pixels formats | expand |
Hi Benjamin,
I love your patch! Perhaps something to improve:
[auto build test WARNING on media-tree/master]
[also build test WARNING on sailus-media-tree/streams linus/master v6.2-rc3 next-20230113]
[cannot apply to pza/reset/next pza/imx-drm/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Benjamin-Gaignard/media-verisilicon-HEVC-Only-propose-10-bits-compatible-pixels-formats/20230113-181802
base: git://linuxtv.org/media_tree.git master
patch link: https://lore.kernel.org/r/20230113101604.261429-1-benjamin.gaignard%40collabora.com
patch subject: [PATCH] media: verisilicon: HEVC: Only propose 10 bits compatible pixels formats
config: m68k-allmodconfig
compiler: m68k-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/94cdfade7a2a05c033dfe7cb9b56dbf748f1f534
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Benjamin-Gaignard/media-verisilicon-HEVC-Only-propose-10-bits-compatible-pixels-formats/20230113-181802
git checkout 94cdfade7a2a05c033dfe7cb9b56dbf748f1f534
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=m68k olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=m68k SHELL=/bin/bash drivers/media/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
drivers/media/platform/verisilicon/hantro_drv.c: In function 'hantro_try_ctrl':
>> drivers/media/platform/verisilicon/hantro_drv.c:254:28: warning: variable 'ctx' set but not used [-Wunused-but-set-variable]
254 | struct hantro_ctx *ctx;
| ^~~
vim +/ctx +254 drivers/media/platform/verisilicon/hantro_drv.c
775fec69008d30 drivers/staging/media/rockchip/vpu/rockchip_vpu_drv.c Ezequiel Garcia 2018-12-05 251
d70cca73234420 drivers/staging/media/hantro/hantro_drv.c Ezequiel Garcia 2020-07-09 252 static int hantro_try_ctrl(struct v4l2_ctrl *ctrl)
d70cca73234420 drivers/staging/media/hantro/hantro_drv.c Ezequiel Garcia 2020-07-09 253 {
4bec03301ecd81 drivers/media/platform/verisilicon/hantro_drv.c Benjamin Gaignard 2022-08-29 @254 struct hantro_ctx *ctx;
4bec03301ecd81 drivers/media/platform/verisilicon/hantro_drv.c Benjamin Gaignard 2022-08-29 255
4bec03301ecd81 drivers/media/platform/verisilicon/hantro_drv.c Benjamin Gaignard 2022-08-29 256 ctx = container_of(ctrl->handler,
4bec03301ecd81 drivers/media/platform/verisilicon/hantro_drv.c Benjamin Gaignard 2022-08-29 257 struct hantro_ctx, ctrl_handler);
4bec03301ecd81 drivers/media/platform/verisilicon/hantro_drv.c Benjamin Gaignard 2022-08-29 258
46a309d2751787 drivers/staging/media/hantro/hantro_drv.c Ezequiel Garcia 2020-11-26 259 if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) {
d70cca73234420 drivers/staging/media/hantro/hantro_drv.c Ezequiel Garcia 2020-07-09 260 const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
d70cca73234420 drivers/staging/media/hantro/hantro_drv.c Ezequiel Garcia 2020-07-09 261
d70cca73234420 drivers/staging/media/hantro/hantro_drv.c Ezequiel Garcia 2020-07-09 262 if (sps->chroma_format_idc > 1)
d70cca73234420 drivers/staging/media/hantro/hantro_drv.c Ezequiel Garcia 2020-07-09 263 /* Only 4:0:0 and 4:2:0 are supported */
d70cca73234420 drivers/staging/media/hantro/hantro_drv.c Ezequiel Garcia 2020-07-09 264 return -EINVAL;
d70cca73234420 drivers/staging/media/hantro/hantro_drv.c Ezequiel Garcia 2020-07-09 265 if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
d70cca73234420 drivers/staging/media/hantro/hantro_drv.c Ezequiel Garcia 2020-07-09 266 /* Luma and chroma bit depth mismatch */
d70cca73234420 drivers/staging/media/hantro/hantro_drv.c Ezequiel Garcia 2020-07-09 267 return -EINVAL;
d70cca73234420 drivers/staging/media/hantro/hantro_drv.c Ezequiel Garcia 2020-07-09 268 if (sps->bit_depth_luma_minus8 != 0)
d70cca73234420 drivers/staging/media/hantro/hantro_drv.c Ezequiel Garcia 2020-07-09 269 /* Only 8-bit is supported */
d70cca73234420 drivers/staging/media/hantro/hantro_drv.c Ezequiel Garcia 2020-07-09 270 return -EINVAL;
b92de2f91821ce drivers/staging/media/hantro/hantro_drv.c Benjamin Gaignard 2022-07-08 271 } else if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) {
8968cfc282955c drivers/staging/media/hantro/hantro_drv.c Benjamin Gaignard 2021-06-03 272 const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
8968cfc282955c drivers/staging/media/hantro/hantro_drv.c Benjamin Gaignard 2021-06-03 273
d040a24b5aaede drivers/media/platform/verisilicon/hantro_drv.c Benjamin Gaignard 2022-08-29 274 if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
d040a24b5aaede drivers/media/platform/verisilicon/hantro_drv.c Benjamin Gaignard 2022-08-29 275 /* Only 8-bit and 10-bit are supported */
df9ec2fc8e70e0 drivers/staging/media/hantro/hantro_drv.c Ezequiel Garcia 2022-07-18 276 return -EINVAL;
e2da465455ce48 drivers/staging/media/hantro/hantro_drv.c Andrzej Pietrasiewicz 2021-11-16 277 } else if (ctrl->id == V4L2_CID_STATELESS_VP9_FRAME) {
e2da465455ce48 drivers/staging/media/hantro/hantro_drv.c Andrzej Pietrasiewicz 2021-11-16 278 const struct v4l2_ctrl_vp9_frame *dec_params = ctrl->p_new.p_vp9_frame;
e2da465455ce48 drivers/staging/media/hantro/hantro_drv.c Andrzej Pietrasiewicz 2021-11-16 279
e2da465455ce48 drivers/staging/media/hantro/hantro_drv.c Andrzej Pietrasiewicz 2021-11-16 280 /* We only support profile 0 */
e2da465455ce48 drivers/staging/media/hantro/hantro_drv.c Andrzej Pietrasiewicz 2021-11-16 281 if (dec_params->profile != 0)
e2da465455ce48 drivers/staging/media/hantro/hantro_drv.c Andrzej Pietrasiewicz 2021-11-16 282 return -EINVAL;
d70cca73234420 drivers/staging/media/hantro/hantro_drv.c Ezequiel Garcia 2020-07-09 283 }
d70cca73234420 drivers/staging/media/hantro/hantro_drv.c Ezequiel Garcia 2020-07-09 284 return 0;
d70cca73234420 drivers/staging/media/hantro/hantro_drv.c Ezequiel Garcia 2020-07-09 285 }
d70cca73234420 drivers/staging/media/hantro/hantro_drv.c Ezequiel Garcia 2020-07-09 286
Le vendredi 13 janvier 2023 à 11:16 +0100, Benjamin Gaignard a écrit : > When decoding a 10bits bitstreams HEVC driver should only expose > 10bits pixel formats. > To fulfill this requirement it is needed to call hantro_reset_raw_fmt() > when bit depth change and to correctly set match_depth in pixel formats > enumeration. > > Fixes: dc39473d0340 ("media: hantro: imx8m: Enable 10bit decoding") > > Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> Tested with 8bit tiled / P010 linear, as that's what we have in GStreamer upstream and it fixed the badly selected format issue. No fluster hack was used. Fluster score was: 141 / 147 Tested-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> > --- > .../media/platform/verisilicon/hantro_drv.c | 35 +++++++++++++++++-- > .../media/platform/verisilicon/hantro_v4l2.c | 2 +- > .../media/platform/verisilicon/hantro_v4l2.h | 1 + > .../media/platform/verisilicon/imx8m_vpu_hw.c | 2 ++ > 4 files changed, 36 insertions(+), 4 deletions(-) > > diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c > index 8cb4a68c9119..78ea05294004 100644 > --- a/drivers/media/platform/verisilicon/hantro_drv.c > +++ b/drivers/media/platform/verisilicon/hantro_drv.c > @@ -274,8 +274,6 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) > if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) > /* Only 8-bit and 10-bit are supported */ > return -EINVAL; > - > - ctx->bit_depth = sps->bit_depth_luma_minus8 + 8; > } else if (ctrl->id == V4L2_CID_STATELESS_VP9_FRAME) { > const struct v4l2_ctrl_vp9_frame *dec_params = ctrl->p_new.p_vp9_frame; > > @@ -286,6 +284,32 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) > return 0; > } > > +static int hantro_hevc_s_ctrl(struct v4l2_ctrl *ctrl) > +{ > + struct hantro_ctx *ctx; > + > + ctx = container_of(ctrl->handler, > + struct hantro_ctx, ctrl_handler); > + > + vpu_debug(1, "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val); > + > + switch (ctrl->id) { > + case V4L2_CID_STATELESS_HEVC_SPS: > + const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; > + int bit_depth = sps->bit_depth_luma_minus8 + 8; > + > + if (ctx->bit_depth != bit_depth) { > + ctx->bit_depth = bit_depth; > + hantro_reset_raw_fmt(ctx); > + } > + break; > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + > static int hantro_jpeg_s_ctrl(struct v4l2_ctrl *ctrl) > { > struct hantro_ctx *ctx; > @@ -328,6 +352,11 @@ static const struct v4l2_ctrl_ops hantro_ctrl_ops = { > .try_ctrl = hantro_try_ctrl, > }; > > +static const struct v4l2_ctrl_ops hantro_hevc_ctrl_ops = { > + .s_ctrl = hantro_hevc_s_ctrl, > + .try_ctrl = hantro_try_ctrl, > +}; > + > static const struct v4l2_ctrl_ops hantro_jpeg_ctrl_ops = { > .s_ctrl = hantro_jpeg_s_ctrl, > }; > @@ -470,7 +499,7 @@ static const struct hantro_ctrl controls[] = { > .codec = HANTRO_HEVC_DECODER, > .cfg = { > .id = V4L2_CID_STATELESS_HEVC_SPS, > - .ops = &hantro_ctrl_ops, > + .ops = &hantro_hevc_ctrl_ops, > }, > }, { > .codec = HANTRO_HEVC_DECODER, > diff --git a/drivers/media/platform/verisilicon/hantro_v4l2.c b/drivers/media/platform/verisilicon/hantro_v4l2.c > index 2c7a805289e7..0025e049dd26 100644 > --- a/drivers/media/platform/verisilicon/hantro_v4l2.c > +++ b/drivers/media/platform/verisilicon/hantro_v4l2.c > @@ -398,7 +398,7 @@ hantro_reset_encoded_fmt(struct hantro_ctx *ctx) > hantro_set_fmt_out(ctx, fmt); > } > > -static void > +void > hantro_reset_raw_fmt(struct hantro_ctx *ctx) > { > const struct hantro_fmt *raw_vpu_fmt; > diff --git a/drivers/media/platform/verisilicon/hantro_v4l2.h b/drivers/media/platform/verisilicon/hantro_v4l2.h > index 64f6f57e9d7a..f642560aed93 100644 > --- a/drivers/media/platform/verisilicon/hantro_v4l2.h > +++ b/drivers/media/platform/verisilicon/hantro_v4l2.h > @@ -21,6 +21,7 @@ > extern const struct v4l2_ioctl_ops hantro_ioctl_ops; > extern const struct vb2_ops hantro_queue_ops; > > +void hantro_reset_raw_fmt(struct hantro_ctx *ctx); > void hantro_reset_fmts(struct hantro_ctx *ctx); > int hantro_get_format_depth(u32 fourcc); > const struct hantro_fmt * > diff --git a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c > index b390228fd3b4..f850d8bddef6 100644 > --- a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c > +++ b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c > @@ -152,6 +152,7 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = { > { > .fourcc = V4L2_PIX_FMT_NV12, > .codec_mode = HANTRO_MODE_NONE, > + .match_depth = true, > .postprocessed = true, > .frmsize = { > .min_width = FMT_MIN_WIDTH, > @@ -165,6 +166,7 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = { > { > .fourcc = V4L2_PIX_FMT_P010, > .codec_mode = HANTRO_MODE_NONE, > + .match_depth = true, > .postprocessed = true, > .frmsize = { > .min_width = FMT_MIN_WIDTH,
diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c index 8cb4a68c9119..78ea05294004 100644 --- a/drivers/media/platform/verisilicon/hantro_drv.c +++ b/drivers/media/platform/verisilicon/hantro_drv.c @@ -274,8 +274,6 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) /* Only 8-bit and 10-bit are supported */ return -EINVAL; - - ctx->bit_depth = sps->bit_depth_luma_minus8 + 8; } else if (ctrl->id == V4L2_CID_STATELESS_VP9_FRAME) { const struct v4l2_ctrl_vp9_frame *dec_params = ctrl->p_new.p_vp9_frame; @@ -286,6 +284,32 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) return 0; } +static int hantro_hevc_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct hantro_ctx *ctx; + + ctx = container_of(ctrl->handler, + struct hantro_ctx, ctrl_handler); + + vpu_debug(1, "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val); + + switch (ctrl->id) { + case V4L2_CID_STATELESS_HEVC_SPS: + const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; + int bit_depth = sps->bit_depth_luma_minus8 + 8; + + if (ctx->bit_depth != bit_depth) { + ctx->bit_depth = bit_depth; + hantro_reset_raw_fmt(ctx); + } + break; + default: + return -EINVAL; + } + + return 0; +} + static int hantro_jpeg_s_ctrl(struct v4l2_ctrl *ctrl) { struct hantro_ctx *ctx; @@ -328,6 +352,11 @@ static const struct v4l2_ctrl_ops hantro_ctrl_ops = { .try_ctrl = hantro_try_ctrl, }; +static const struct v4l2_ctrl_ops hantro_hevc_ctrl_ops = { + .s_ctrl = hantro_hevc_s_ctrl, + .try_ctrl = hantro_try_ctrl, +}; + static const struct v4l2_ctrl_ops hantro_jpeg_ctrl_ops = { .s_ctrl = hantro_jpeg_s_ctrl, }; @@ -470,7 +499,7 @@ static const struct hantro_ctrl controls[] = { .codec = HANTRO_HEVC_DECODER, .cfg = { .id = V4L2_CID_STATELESS_HEVC_SPS, - .ops = &hantro_ctrl_ops, + .ops = &hantro_hevc_ctrl_ops, }, }, { .codec = HANTRO_HEVC_DECODER, diff --git a/drivers/media/platform/verisilicon/hantro_v4l2.c b/drivers/media/platform/verisilicon/hantro_v4l2.c index 2c7a805289e7..0025e049dd26 100644 --- a/drivers/media/platform/verisilicon/hantro_v4l2.c +++ b/drivers/media/platform/verisilicon/hantro_v4l2.c @@ -398,7 +398,7 @@ hantro_reset_encoded_fmt(struct hantro_ctx *ctx) hantro_set_fmt_out(ctx, fmt); } -static void +void hantro_reset_raw_fmt(struct hantro_ctx *ctx) { const struct hantro_fmt *raw_vpu_fmt; diff --git a/drivers/media/platform/verisilicon/hantro_v4l2.h b/drivers/media/platform/verisilicon/hantro_v4l2.h index 64f6f57e9d7a..f642560aed93 100644 --- a/drivers/media/platform/verisilicon/hantro_v4l2.h +++ b/drivers/media/platform/verisilicon/hantro_v4l2.h @@ -21,6 +21,7 @@ extern const struct v4l2_ioctl_ops hantro_ioctl_ops; extern const struct vb2_ops hantro_queue_ops; +void hantro_reset_raw_fmt(struct hantro_ctx *ctx); void hantro_reset_fmts(struct hantro_ctx *ctx); int hantro_get_format_depth(u32 fourcc); const struct hantro_fmt * diff --git a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c index b390228fd3b4..f850d8bddef6 100644 --- a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c +++ b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c @@ -152,6 +152,7 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = { { .fourcc = V4L2_PIX_FMT_NV12, .codec_mode = HANTRO_MODE_NONE, + .match_depth = true, .postprocessed = true, .frmsize = { .min_width = FMT_MIN_WIDTH, @@ -165,6 +166,7 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = { { .fourcc = V4L2_PIX_FMT_P010, .codec_mode = HANTRO_MODE_NONE, + .match_depth = true, .postprocessed = true, .frmsize = { .min_width = FMT_MIN_WIDTH,
When decoding a 10bits bitstreams HEVC driver should only expose 10bits pixel formats. To fulfill this requirement it is needed to call hantro_reset_raw_fmt() when bit depth change and to correctly set match_depth in pixel formats enumeration. Fixes: dc39473d0340 ("media: hantro: imx8m: Enable 10bit decoding") Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> --- .../media/platform/verisilicon/hantro_drv.c | 35 +++++++++++++++++-- .../media/platform/verisilicon/hantro_v4l2.c | 2 +- .../media/platform/verisilicon/hantro_v4l2.h | 1 + .../media/platform/verisilicon/imx8m_vpu_hw.c | 2 ++ 4 files changed, 36 insertions(+), 4 deletions(-)