From patchwork Wed Jan 25 17:27:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 13115889 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 033C9C54E94 for ; Wed, 25 Jan 2023 17:28:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=h17UwLEhvrwXiP8XSuTmgQzoKQ63MCuEZKUmu9rIkCo=; b=3yiBPNe2nHk+6G 3r9ons+AqL8DJRmerUCjngdpm8SVV7Spva29oDn72Yrx/Z5WKIOa7+vICIrwZCDyXH0pg4EhUf5NF qLmGm5BBOKfML/VZuBgFvZu8Z6prP7Rf4df9UfGWb5brZtj0LN8osBzAj1YJoTYQOzgvqlYWc/cXh deGoHuP9eW1UmWi3MlhSXyi+XKyqrH1ISifGCEzwWzjvA+TT3RILpf3CuQeH0OFHYbApzmfQVrN3u oMoYc8RXOumLo1norzE6+jw5ZKGJfduCtM/GOPu5Ov6YpMsAHt0XtZi2jAzfECPMTKdZWy+MnzDBg 6Sufz62N4+mSHQ7X2B8Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pKjZU-008CKO-BX; Wed, 25 Jan 2023 17:28:28 +0000 Received: from madras.collabora.co.uk ([2a00:1098:0:82:1000:25:2eeb:e5ab]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pKjZ8-008CCL-UL; Wed, 25 Jan 2023 17:28:08 +0000 Received: from benjamin-XPS-13-9310.. (unknown [IPv6:2a01:e0a:120:3210:ad6f:c6af:709d:745c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: benjamin.gaignard) by madras.collabora.co.uk (Postfix) with ESMTPSA id 7FF766602E6B; Wed, 25 Jan 2023 17:28:03 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1674667683; bh=UHN+nMs+n4jX7nk2ZzasYi5PAlhbZHRCrcYcr8lRebA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I1szdJ9lC4AAKuPFpGQI7T1K3ti7RHHil3Bu5WfSZomIMrn2o8GPyb/QHSEd1TdZA iDjE9JcVNOvcByd57GM3DwsCqIRZL4c4Z5ZgpIZ2yVj4xQFZ7zAusng1C31iCdQvWb 7ROxHwQemOXEP1XxoN79/QA9r5NUj2bhjrsnf6n1BVisMfLMd5DPX0NhTOrXN5M6QA 59PIRKO2Jnpy71cquvWqvV/1cAgoh2Sya/R+tU1aghGKytd9lQnTLRLxVn+DDgHmNe 6WWRHohD08Q7QEWiPGndXseBX9TaY+6D2CVmAWO7jC0bA7R/2OMNz7BMTyRHyihRxZ 6/myLYfkOd6uA== From: Benjamin Gaignard To: ezequiel@vanguardiasur.com.ar, p.zabel@pengutronix.de, mchehab@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, hverkuil-cisco@xs4all.nl, nicolas.dufresne@collabora.co.uk Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, Benjamin Gaignard Subject: [PATCH v4 2/2] media: verisilicon: HEVC: Only propose 10 bits compatible pixels formats Date: Wed, 25 Jan 2023 18:27:55 +0100 Message-Id: <20230125172755.1498973-3-benjamin.gaignard@collabora.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230125172755.1498973-1-benjamin.gaignard@collabora.com> References: <20230125172755.1498973-1-benjamin.gaignard@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230125_092807_298183_289AECA0 X-CRM114-Status: GOOD ( 16.98 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org When decoding a 10bits bitstreams HEVC driver should only expose 10bits pixel formats. To fulfill this requirement it is needed to call hantro_reset_raw_fmt() when bit depth change and to correctly set match_depth in pixel formats enumeration. Signed-off-by: Benjamin Gaignard Reviewed-by: Nicolas Dufresne --- version 4: - Only set ctx->bit_depth when hantro_reset_raw_fmt() returns is ok. .../media/platform/verisilicon/hantro_drv.c | 46 +++++++++++++++---- .../media/platform/verisilicon/imx8m_vpu_hw.c | 2 + 2 files changed, 40 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c index 8cb4a68c9119..30abab7ac9bf 100644 --- a/drivers/media/platform/verisilicon/hantro_drv.c +++ b/drivers/media/platform/verisilicon/hantro_drv.c @@ -251,11 +251,6 @@ queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) { - struct hantro_ctx *ctx; - - ctx = container_of(ctrl->handler, - struct hantro_ctx, ctrl_handler); - if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) { const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; @@ -274,8 +269,6 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) /* Only 8-bit and 10-bit are supported */ return -EINVAL; - - ctx->bit_depth = sps->bit_depth_luma_minus8 + 8; } else if (ctrl->id == V4L2_CID_STATELESS_VP9_FRAME) { const struct v4l2_ctrl_vp9_frame *dec_params = ctrl->p_new.p_vp9_frame; @@ -286,6 +279,38 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) return 0; } +static int hantro_hevc_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct hantro_ctx *ctx; + + ctx = container_of(ctrl->handler, + struct hantro_ctx, ctrl_handler); + + vpu_debug(1, "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val); + + switch (ctrl->id) { + case V4L2_CID_STATELESS_HEVC_SPS: + { + const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; + int bit_depth = sps->bit_depth_luma_minus8 + 8; + int ret; + + if (ctx->bit_depth == bit_depth) + return 0; + + ret = hantro_reset_raw_fmt(ctx, bit_depth); + if (!ret) + ctx->bit_depth = bit_depth; + + return ret; + } + default: + return -EINVAL; + } + + return 0; +} + static int hantro_jpeg_s_ctrl(struct v4l2_ctrl *ctrl) { struct hantro_ctx *ctx; @@ -328,6 +353,11 @@ static const struct v4l2_ctrl_ops hantro_ctrl_ops = { .try_ctrl = hantro_try_ctrl, }; +static const struct v4l2_ctrl_ops hantro_hevc_ctrl_ops = { + .s_ctrl = hantro_hevc_s_ctrl, + .try_ctrl = hantro_try_ctrl, +}; + static const struct v4l2_ctrl_ops hantro_jpeg_ctrl_ops = { .s_ctrl = hantro_jpeg_s_ctrl, }; @@ -470,7 +500,7 @@ static const struct hantro_ctrl controls[] = { .codec = HANTRO_HEVC_DECODER, .cfg = { .id = V4L2_CID_STATELESS_HEVC_SPS, - .ops = &hantro_ctrl_ops, + .ops = &hantro_hevc_ctrl_ops, }, }, { .codec = HANTRO_HEVC_DECODER, diff --git a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c index b390228fd3b4..f850d8bddef6 100644 --- a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c +++ b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c @@ -152,6 +152,7 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = { { .fourcc = V4L2_PIX_FMT_NV12, .codec_mode = HANTRO_MODE_NONE, + .match_depth = true, .postprocessed = true, .frmsize = { .min_width = FMT_MIN_WIDTH, @@ -165,6 +166,7 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = { { .fourcc = V4L2_PIX_FMT_P010, .codec_mode = HANTRO_MODE_NONE, + .match_depth = true, .postprocessed = true, .frmsize = { .min_width = FMT_MIN_WIDTH,