| Message ID | 20230203091622.127279-6-benjamin.gaignard@collabora.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | media: verisilicon: HEVC: fix 10bits handling | expand |
Hi Benjamin, On Fri, Feb 3 2023 at 10:16:21 AM +0100, Benjamin Gaignard <benjamin.gaignard@collabora.com> wrote: > When decoding a 10bits bitstreams HEVC driver should only expose > 10bits pixel formats. > To fulfill this requirement it is needed to call > hantro_reset_raw_fmt() > when bit depth change and to correctly set match_depth in pixel > formats > enumeration. > > Fixes: dc39473d0340 ("media: hantro: imx8m: Enable 10bit decoding") > > Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> > Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> > --- > drivers/media/platform/verisilicon/hantro_drv.c | 11 +++++++++-- > drivers/media/platform/verisilicon/imx8m_vpu_hw.c | 2 ++ > 2 files changed, 11 insertions(+), 2 deletions(-) > > diff --git a/drivers/media/platform/verisilicon/hantro_drv.c > b/drivers/media/platform/verisilicon/hantro_drv.c > index 6d8bc55ea627..fa31b200b097 100644 > --- a/drivers/media/platform/verisilicon/hantro_drv.c > +++ b/drivers/media/platform/verisilicon/hantro_drv.c > @@ -326,8 +326,15 @@ static int hantro_hevc_s_ctrl(struct v4l2_ctrl > *ctrl) > > switch (ctrl->id) { > case V4L2_CID_STATELESS_HEVC_SPS: > - ctx->bit_depth = ctrl->p_new.p_hevc_sps->bit_depth_luma_minus8 + 8; > - break; > + { Should be: case V4L2_CID_STATELESS_HEVC_SPS: { ... Same for VP9. Thanks, Ezequiel > + const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; > + int bit_depth = sps->bit_depth_luma_minus8 + 8; > + > + if (ctx->bit_depth == bit_depth) > + return 0; > + > + return hantro_reset_raw_fmt(ctx, bit_depth); > + } > default: > return -EINVAL; > } > diff --git a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c > b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c > index b390228fd3b4..f850d8bddef6 100644 > --- a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c > +++ b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c > @@ -152,6 +152,7 @@ static const struct hantro_fmt > imx8m_vpu_g2_postproc_fmts[] = { > { > .fourcc = V4L2_PIX_FMT_NV12, > .codec_mode = HANTRO_MODE_NONE, > + .match_depth = true, > .postprocessed = true, > .frmsize = { > .min_width = FMT_MIN_WIDTH, > @@ -165,6 +166,7 @@ static const struct hantro_fmt > imx8m_vpu_g2_postproc_fmts[] = { > { > .fourcc = V4L2_PIX_FMT_P010, > .codec_mode = HANTRO_MODE_NONE, > + .match_depth = true, > .postprocessed = true, > .frmsize = { > .min_width = FMT_MIN_WIDTH, > -- > 2.34.1 >
diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c index 6d8bc55ea627..fa31b200b097 100644 --- a/drivers/media/platform/verisilicon/hantro_drv.c +++ b/drivers/media/platform/verisilicon/hantro_drv.c @@ -326,8 +326,15 @@ static int hantro_hevc_s_ctrl(struct v4l2_ctrl *ctrl) switch (ctrl->id) { case V4L2_CID_STATELESS_HEVC_SPS: - ctx->bit_depth = ctrl->p_new.p_hevc_sps->bit_depth_luma_minus8 + 8; - break; + { + const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; + int bit_depth = sps->bit_depth_luma_minus8 + 8; + + if (ctx->bit_depth == bit_depth) + return 0; + + return hantro_reset_raw_fmt(ctx, bit_depth); + } default: return -EINVAL; } diff --git a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c index b390228fd3b4..f850d8bddef6 100644 --- a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c +++ b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c @@ -152,6 +152,7 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = { { .fourcc = V4L2_PIX_FMT_NV12, .codec_mode = HANTRO_MODE_NONE, + .match_depth = true, .postprocessed = true, .frmsize = { .min_width = FMT_MIN_WIDTH, @@ -165,6 +166,7 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = { { .fourcc = V4L2_PIX_FMT_P010, .codec_mode = HANTRO_MODE_NONE, + .match_depth = true, .postprocessed = true, .frmsize = { .min_width = FMT_MIN_WIDTH,
When decoding a 10bits bitstreams HEVC driver should only expose 10bits pixel formats. To fulfill this requirement it is needed to call hantro_reset_raw_fmt() when bit depth change and to correctly set match_depth in pixel formats enumeration. Fixes: dc39473d0340 ("media: hantro: imx8m: Enable 10bit decoding") Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> --- drivers/media/platform/verisilicon/hantro_drv.c | 11 +++++++++-- drivers/media/platform/verisilicon/imx8m_vpu_hw.c | 2 ++ 2 files changed, 11 insertions(+), 2 deletions(-)