| Message ID | 20230505113856.463650-10-s.hauer@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add perf support to the rockchip-dfi driver | expand |
On Fri, 5 May 2023 13:38:44 +0200 Sascha Hauer <s.hauer@pengutronix.de> wrote: > Use the HIWORD_UPDATE() define known from other rockchip drivers to > make the defines look less odd to the readers who've seen other > rockchip drivers. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Whilst this might be fine, it's not a noop change. So more text needed to explain why it's fine to write the same 'mask' always when previously only single bits were set in the mask. > --- > drivers/devfreq/event/rockchip-dfi.c | 32 +++++++++++++++++----------- > 1 file changed, 20 insertions(+), 12 deletions(-) > > diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c > index 7896cd8beb143..035984d3c7b01 100644 > --- a/drivers/devfreq/event/rockchip-dfi.c > +++ b/drivers/devfreq/event/rockchip-dfi.c > @@ -26,15 +26,19 @@ > > #define DMC_MAX_CHANNELS 2 > > +#define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16) > + > /* DDRMON_CTRL */ > #define DDRMON_CTRL 0x04 > -#define CLR_DDRMON_CTRL (0x1f0000 << 0) > -#define LPDDR4_EN (0x10001 << 4) > -#define HARDWARE_EN (0x10001 << 3) > -#define LPDDR3_EN (0x10001 << 2) > -#define SOFTWARE_EN (0x10001 << 1) > -#define SOFTWARE_DIS (0x10000 << 1) > -#define TIME_CNT_EN (0x10001 << 0) > +#define DDRMON_CTRL_DDR4 BIT(5) > +#define DDRMON_CTRL_LPDDR4 BIT(4) > +#define DDRMON_CTRL_HARDWARE_EN BIT(3) > +#define DDRMON_CTRL_LPDDR23 BIT(2) > +#define DDRMON_CTRL_SOFTWARE_EN BIT(1) > +#define DDRMON_CTRL_TIMER_CNT_EN BIT(0) > +#define DDRMON_CTRL_DDR_TYPE_MASK (DDRMON_CTRL_DDR4 | \ > + DDRMON_CTRL_LPDDR4 | \ > + DDRMON_CTRL_LPDDR23) > > #define DDRMON_CH0_COUNT_NUM 0x28 > #define DDRMON_CH0_DFI_ACCESS_NUM 0x2c > @@ -74,16 +78,19 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) > void __iomem *dfi_regs = dfi->regs; > > /* clear DDRMON_CTRL setting */ > - writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL); > + writel_relaxed(HIWORD_UPDATE(0, 0xffff), dfi_regs + DDRMON_CTRL); > > /* set ddr type to dfi */ > if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3) > - writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL); > + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK), > + dfi_regs + DDRMON_CTRL); > else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4) > - writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL); Old value written is 0x10001 << 4 == 0x100010 > + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK), > + dfi_regs + DDRMON_CTRL); New value is (BIT(5) | BIT(4) | BIT(2)) | (BIT(4) << 16) 0x100034 >
On Tue, May 16, 2023 at 05:01:46PM +0100, Jonathan Cameron wrote: > On Fri, 5 May 2023 13:38:44 +0200 > Sascha Hauer <s.hauer@pengutronix.de> wrote: > > > Use the HIWORD_UPDATE() define known from other rockchip drivers to > > make the defines look less odd to the readers who've seen other > > rockchip drivers. > > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > Whilst this might be fine, it's not a noop change. So more > text needed to explain why it's fine to write the same 'mask' always > when previously only single bits were set in the mask. > > > --- > > drivers/devfreq/event/rockchip-dfi.c | 32 +++++++++++++++++----------- > > 1 file changed, 20 insertions(+), 12 deletions(-) > > > > diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c > > index 7896cd8beb143..035984d3c7b01 100644 > > --- a/drivers/devfreq/event/rockchip-dfi.c > > +++ b/drivers/devfreq/event/rockchip-dfi.c > > @@ -26,15 +26,19 @@ > > > > #define DMC_MAX_CHANNELS 2 > > > > +#define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16) > > + > > /* DDRMON_CTRL */ > > #define DDRMON_CTRL 0x04 > > -#define CLR_DDRMON_CTRL (0x1f0000 << 0) > > -#define LPDDR4_EN (0x10001 << 4) > > -#define HARDWARE_EN (0x10001 << 3) > > -#define LPDDR3_EN (0x10001 << 2) > > -#define SOFTWARE_EN (0x10001 << 1) > > -#define SOFTWARE_DIS (0x10000 << 1) > > -#define TIME_CNT_EN (0x10001 << 0) > > +#define DDRMON_CTRL_DDR4 BIT(5) > > +#define DDRMON_CTRL_LPDDR4 BIT(4) > > +#define DDRMON_CTRL_HARDWARE_EN BIT(3) > > +#define DDRMON_CTRL_LPDDR23 BIT(2) > > +#define DDRMON_CTRL_SOFTWARE_EN BIT(1) > > +#define DDRMON_CTRL_TIMER_CNT_EN BIT(0) > > +#define DDRMON_CTRL_DDR_TYPE_MASK (DDRMON_CTRL_DDR4 | \ > > + DDRMON_CTRL_LPDDR4 | \ > > + DDRMON_CTRL_LPDDR23) > > > > #define DDRMON_CH0_COUNT_NUM 0x28 > > #define DDRMON_CH0_DFI_ACCESS_NUM 0x2c > > @@ -74,16 +78,19 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) > > void __iomem *dfi_regs = dfi->regs; > > > > /* clear DDRMON_CTRL setting */ > > - writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL); > > + writel_relaxed(HIWORD_UPDATE(0, 0xffff), dfi_regs + DDRMON_CTRL); > > > > /* set ddr type to dfi */ > > if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3) > > - writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL); > > + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK), > > + dfi_regs + DDRMON_CTRL); > > else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4) > > - writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL); > Old value written is 0x10001 << 4 == 0x100010 > > + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK), > > + dfi_regs + DDRMON_CTRL); > New value is (BIT(5) | BIT(4) | BIT(2)) | (BIT(4) << 16) > 0x100034 Actually it's (BIT(5) | BIT(4) | BIT(2)) << 16 | BIT(4) = 0x340010 The hiword registers contain a mask in the upper 16 bits and functional bits in the lower 16 bits. When writing to them only the functional bits that have the corresponding mask bits set are modified, the others stay untouched. Previously we had: writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL); writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL); The first access clears the lower 5 bits and the second sets BIT(4) This now becomes: writel_relaxed(HIWORD_UPDATE(0, 0xffff), dfi_regs + DDRMON_CTRL); writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK), dfi_regs + DDRMON_CTRL); The first access clears the lower 16 bits and the second sets BIT(4) That's both identical except that my version clears the lower 16 bits instead of lower 5 bits. I'll see if I can make that a bit clearer in the commit message. Sascha
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index 7896cd8beb143..035984d3c7b01 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -26,15 +26,19 @@ #define DMC_MAX_CHANNELS 2 +#define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16) + /* DDRMON_CTRL */ #define DDRMON_CTRL 0x04 -#define CLR_DDRMON_CTRL (0x1f0000 << 0) -#define LPDDR4_EN (0x10001 << 4) -#define HARDWARE_EN (0x10001 << 3) -#define LPDDR3_EN (0x10001 << 2) -#define SOFTWARE_EN (0x10001 << 1) -#define SOFTWARE_DIS (0x10000 << 1) -#define TIME_CNT_EN (0x10001 << 0) +#define DDRMON_CTRL_DDR4 BIT(5) +#define DDRMON_CTRL_LPDDR4 BIT(4) +#define DDRMON_CTRL_HARDWARE_EN BIT(3) +#define DDRMON_CTRL_LPDDR23 BIT(2) +#define DDRMON_CTRL_SOFTWARE_EN BIT(1) +#define DDRMON_CTRL_TIMER_CNT_EN BIT(0) +#define DDRMON_CTRL_DDR_TYPE_MASK (DDRMON_CTRL_DDR4 | \ + DDRMON_CTRL_LPDDR4 | \ + DDRMON_CTRL_LPDDR23) #define DDRMON_CH0_COUNT_NUM 0x28 #define DDRMON_CH0_DFI_ACCESS_NUM 0x2c @@ -74,16 +78,19 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) void __iomem *dfi_regs = dfi->regs; /* clear DDRMON_CTRL setting */ - writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL); + writel_relaxed(HIWORD_UPDATE(0, 0xffff), dfi_regs + DDRMON_CTRL); /* set ddr type to dfi */ if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3) - writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL); + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK), + dfi_regs + DDRMON_CTRL); else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4) - writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL); + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK), + dfi_regs + DDRMON_CTRL); /* enable count, use software mode */ - writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL); + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN), + dfi_regs + DDRMON_CTRL); } static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev) @@ -91,7 +98,8 @@ static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev) struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev); void __iomem *dfi_regs = dfi->regs; - writel_relaxed(SOFTWARE_DIS, dfi_regs + DDRMON_CTRL); + writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN), + dfi_regs + DDRMON_CTRL); } static void rockchip_dfi_read_counters(struct devfreq_event_dev *edev, struct dmc_count *count)
Use the HIWORD_UPDATE() define known from other rockchip drivers to make the defines look less odd to the readers who've seen other rockchip drivers. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- drivers/devfreq/event/rockchip-dfi.c | 32 +++++++++++++++++----------- 1 file changed, 20 insertions(+), 12 deletions(-)