| Message ID | 20230714175331.112923-2-sebastian.reichel@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | RK3588 PCIe3 support | expand |
On Fri, Jul 14, 2023 at 07:53:30PM +0200, Sebastian Reichel wrote: > When the RK3568 PCIe v3 PHY supported has been upstreamed, RK3588 > support was included, but the DT binding does not reflect this. > This adds the missing bits. Thanks for rectifying that! Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml index 9f2d8d2cc7a5..c4fbffcde6e4 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml @@ -13,19 +13,18 @@ properties: compatible: enum: - rockchip,rk3568-pcie3-phy + - rockchip,rk3588-pcie3-phy reg: maxItems: 1 clocks: - minItems: 3 + minItems: 1 maxItems: 3 clock-names: - items: - - const: refclk_m - - const: refclk_n - - const: pclk + minItems: 1 + maxItems: 3 data-lanes: description: which lanes (by position) should be mapped to which @@ -61,6 +60,30 @@ required: - rockchip,phy-grf - "#phy-cells" +allOf: + - if: + properties: + compatible: + enum: + - rockchip,rk3588-pcie3-phy + then: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: pclk + else: + properties: + clocks: + minItems: 3 + + clock-names: + items: + - const: refclk_m + - const: refclk_n + - const: pclk + additionalProperties: false examples:
When the RK3568 PCIe v3 PHY supported has been upstreamed, RK3588 support was included, but the DT binding does not reflect this. This adds the missing bits. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> --- .../bindings/phy/rockchip,pcie3-phy.yaml | 33 ++++++++++++++++--- 1 file changed, 28 insertions(+), 5 deletions(-)