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Mon, 31 Jul 2023 04:01:07 -0700 (PDT) Received: from localhost.localdomain ([49.205.243.15]) by smtp.gmail.com with ESMTPSA id t14-20020a1709028c8e00b001b1a2c14a4asm8281096plo.38.2023.07.31.04.01.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jul 2023 04:01:06 -0700 (PDT) From: Jagan Teki To: Heiko Stuebner , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Cc: Jagan Teki , devicetree@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH 12/14] ARM: dts: rockchip: rv1126: Add Edgeble Neu2 IO DSI overlay Date: Mon, 31 Jul 2023 16:30:10 +0530 Message-Id: <20230731110012.2913742-13-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230731110012.2913742-1-jagan@edgeble.ai> References: <20230731110012.2913742-1-jagan@edgeble.ai> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230731_040108_253343_F1CDC9C2 X-CRM114-Status: GOOD ( 14.80 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Add DSI pipeline for Edgeble Neu2 IO board via DT-overlay The DSI connector in Edgeble Neu2 IO board support different resolution panels and those compatible is added in another DT-overlay. Add Edgeble Neu2 IO DSI connector DT-overlay. Signed-off-by: Jagan Teki --- Cc: devicetree@vger.kernel.org Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Conor Dooley arch/arm/boot/dts/rockchip/Makefile | 1 + .../rockchip/rv1126-edgeble-neu2-io-dsi.dtso | 112 ++++++++++++++++++ 2 files changed, 113 insertions(+) create mode 100644 arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io-dsi.dtso diff --git a/arch/arm/boot/dts/rockchip/Makefile b/arch/arm/boot/dts/rockchip/Makefile index 0f46e18fe275..c8c8e1292650 100644 --- a/arch/arm/boot/dts/rockchip/Makefile +++ b/arch/arm/boot/dts/rockchip/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rv1108-elgin-r1.dtb \ rv1108-evb.dtb \ rv1126-edgeble-neu2-io.dtb \ + rv1126-edgeble-neu2-io-dsi.dtbo \ rk3036-evb.dtb \ rk3036-kylin.dtb \ rk3066a-bqcurie2.dtb \ diff --git a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io-dsi.dtso b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io-dsi.dtso new file mode 100644 index 000000000000..88431e1e30f8 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io-dsi.dtso @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. + * + * DT-overlay for Edgeble Neu2 IO DSI Connector. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 25000 0>; + enable-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&backlight_en>; + }; + + vcc_lcd_mipi_2: vcc-lcd-mipi-2-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_mipi_2"; + enable-active-high; + gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_lcd_mipi_2_en>; + regulator-boot-on; + vin-supply = <&v3v3_sys>; + }; + + vcc_1v8_2: vcc-1v8-2-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&dsi_dphy { + status = "okay"; +}; + +&dsi { + clock-master; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + + panel: panel@0 { + /* different resolution panels are used, compatibles are in DTO */ + reg = <0>; + vdd-supply = <&vcc_lcd_mipi_2>; + vccio-supply = <&vcc_1v8_2>; + reset-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_reset>; + backlight = <&backlight>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&pinctrl { + lcd { + backlight_en: backlight-en { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + lcd_reset: lcd-reset { + rockchip,pins = <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc_lcd_mipi_2_en: vcc-lcd-mipi-2-en { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +};