@@ -34,6 +34,7 @@ cpu0: cpu@f00 {
reg = <0xf00>;
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
+ resets = <&cru SRST_CORE0>;
operating-points = <
/* KHz uV */
816000 1000000
@@ -45,18 +46,21 @@ cpu1: cpu@f01 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf01>;
+ resets = <&cru SRST_CORE1>;
};
cpu2: cpu@f02 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf02>;
+ resets = <&cru SRST_CORE2>;
};
cpu3: cpu@f03 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf03>;
+ resets = <&cru SRST_CORE3>;
};
};
In order to support bring-up of the non-boot cores, this patch adds the reset controls for the cpu cores. They are required/will be used by the Rockchip platsmp driver. Signed-off-by: Alex Bee <knaerzche@gmail.com> --- arch/arm/boot/dts/rockchip/rk3128.dtsi | 4 ++++ 1 file changed, 4 insertions(+)