diff mbox series

[v1,4/8] clk: rockchip: Avoid __clk_lookup() calls

Message ID 20230918073151.7660-5-zhangqing@rock-chips.com (mailing list archive)
State New, archived
Headers show
Series clk: rockchip: Support module build | expand

Commit Message

zhangqing Sept. 18, 2023, 7:31 a.m. UTC 
clk pointer gets cached in the driver's private data and
can be used later instead of a __clk_lookup() call.

clk provider clk_data.clks[] and we can reference
the clk pointers directly rather than using __clk_lookup()
with global names.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk-cpu.c    | 18 +++++++++++++-----
 drivers/clk/rockchip/clk-px30.c   | 17 +++++++++++------
 drivers/clk/rockchip/clk-rk3036.c |  5 +++--
 drivers/clk/rockchip/clk-rk3128.c |  5 +++--
 drivers/clk/rockchip/clk-rk3188.c | 22 +++++++++++-----------
 drivers/clk/rockchip/clk-rk3228.c |  5 +++--
 drivers/clk/rockchip/clk-rk3288.c |  5 +++--
 drivers/clk/rockchip/clk-rk3308.c |  5 +++--
 drivers/clk/rockchip/clk-rk3328.c |  4 +++-
 drivers/clk/rockchip/clk-rk3368.c |  8 ++++----
 drivers/clk/rockchip/clk-rk3399.c | 14 ++++----------
 drivers/clk/rockchip/clk-rk3568.c |  5 +++--
 drivers/clk/rockchip/clk-rk3588.c |  8 +++++---
 drivers/clk/rockchip/clk-rv1108.c |  5 +++--
 drivers/clk/rockchip/clk-rv1126.c |  8 +++++++-
 drivers/clk/rockchip/clk.c        |  6 ++++--
 drivers/clk/rockchip/clk.h        | 17 ++++++++++-------
 17 files changed, 93 insertions(+), 64 deletions(-)

Comments

kernel test robot Sept. 18, 2023, 1:32 p.m. UTC | #1 
Hi Elaine,

kernel test robot noticed the following build warnings:

[auto build test WARNING on rockchip/for-next]
[also build test WARNING on clk/clk-next linus/master v6.6-rc2 next-20230918]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Elaine-Zhang/clk-clk-fractional-divider-Export-clk_fractional_divider_general_approximation-API/20230918-154652
base:   https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next
patch link:    https://lore.kernel.org/r/20230918073151.7660-5-zhangqing%40rock-chips.com
patch subject: [PATCH v1 4/8] clk: rockchip: Avoid __clk_lookup() calls
config: arm-defconfig (https://download.01.org/0day-ci/archive/20230918/202309182118.ErkxCm5A-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230918/202309182118.ErkxCm5A-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202309182118.ErkxCm5A-lkp@intel.com/

All warnings (new ones prefixed by >>):

   In file included from drivers/clk/rockchip/clk-rv1126.c:14:
>> drivers/clk/rockchip/clk-rv1126.c:157:7: warning: 'mux_armclk_p' defined but not used [-Wunused-const-variable=]
     157 | PNAME(mux_armclk_p)                     = { "gpll", "cpll", "apll" };
         |       ^~~~~~~~~~~~
   drivers/clk/rockchip/clk.h:512:43: note: in definition of macro 'PNAME'
     512 | #define PNAME(x) static const char *const x[] __initconst
         |                                           ^


vim +/mux_armclk_p +157 drivers/clk/rockchip/clk-rv1126.c

2408ab5aa876cb Jagan Teki 2022-09-15  @14  #include "clk.h"
2408ab5aa876cb Jagan Teki 2022-09-15   15  
2408ab5aa876cb Jagan Teki 2022-09-15   16  #define RV1126_GMAC_CON			0x460
2408ab5aa876cb Jagan Teki 2022-09-15   17  #define RV1126_GRF_IOFUNC_CON1		0x10264
2408ab5aa876cb Jagan Teki 2022-09-15   18  #define RV1126_GRF_SOC_STATUS0		0x10
2408ab5aa876cb Jagan Teki 2022-09-15   19  
2408ab5aa876cb Jagan Teki 2022-09-15   20  #define RV1126_FRAC_MAX_PRATE		1200000000
2408ab5aa876cb Jagan Teki 2022-09-15   21  #define RV1126_CSIOUT_FRAC_MAX_PRATE	300000000
2408ab5aa876cb Jagan Teki 2022-09-15   22  
2408ab5aa876cb Jagan Teki 2022-09-15   23  enum rv1126_pmu_plls {
2408ab5aa876cb Jagan Teki 2022-09-15   24  	gpll,
2408ab5aa876cb Jagan Teki 2022-09-15   25  };
2408ab5aa876cb Jagan Teki 2022-09-15   26  
2408ab5aa876cb Jagan Teki 2022-09-15   27  enum rv1126_plls {
2408ab5aa876cb Jagan Teki 2022-09-15   28  	apll, dpll, cpll, hpll,
2408ab5aa876cb Jagan Teki 2022-09-15   29  };
2408ab5aa876cb Jagan Teki 2022-09-15   30  
2408ab5aa876cb Jagan Teki 2022-09-15   31  static struct rockchip_pll_rate_table rv1126_pll_rates[] = {
2408ab5aa876cb Jagan Teki 2022-09-15   32  	/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
2408ab5aa876cb Jagan Teki 2022-09-15   33  	RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   34  	RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   35  	RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   36  	RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   37  	RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   38  	RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   39  	RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   40  	RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   41  	RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   42  	RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   43  	RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   44  	RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   45  	RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   46  	RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   47  	RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   48  	RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   49  	RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   50  	RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   51  	RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   52  	RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   53  	RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   54  	RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   55  	RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   56  	RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   57  	RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   58  	RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   59  	RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   60  	RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   61  	RK3036_PLL_RATE(900000000, 1, 75, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   62  	RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   63  	RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   64  	RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   65  	RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   66  	RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   67  	RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   68  	RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   69  	RK3036_PLL_RATE(624000000, 1, 104, 4, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   70  	RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   71  	RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   72  	RK3036_PLL_RATE(504000000, 1, 84, 4, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   73  	RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   74  	RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   75  	RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   76  	RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   77  	RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
2408ab5aa876cb Jagan Teki 2022-09-15   78  	{ /* sentinel */ },
2408ab5aa876cb Jagan Teki 2022-09-15   79  };
2408ab5aa876cb Jagan Teki 2022-09-15   80  
2408ab5aa876cb Jagan Teki 2022-09-15   81  #define RV1126_DIV_ACLK_CORE_MASK	0xf
2408ab5aa876cb Jagan Teki 2022-09-15   82  #define RV1126_DIV_ACLK_CORE_SHIFT	4
2408ab5aa876cb Jagan Teki 2022-09-15   83  #define RV1126_DIV_PCLK_DBG_MASK	0x7
2408ab5aa876cb Jagan Teki 2022-09-15   84  #define RV1126_DIV_PCLK_DBG_SHIFT	0
2408ab5aa876cb Jagan Teki 2022-09-15   85  
2408ab5aa876cb Jagan Teki 2022-09-15   86  #define RV1126_CLKSEL1(_aclk_core, _pclk_dbg)				\
2408ab5aa876cb Jagan Teki 2022-09-15   87  {									\
2408ab5aa876cb Jagan Teki 2022-09-15   88  	.reg = RV1126_CLKSEL_CON(1),					\
2408ab5aa876cb Jagan Teki 2022-09-15   89  	.val = HIWORD_UPDATE(_aclk_core, RV1126_DIV_ACLK_CORE_MASK,	\
2408ab5aa876cb Jagan Teki 2022-09-15   90  			     RV1126_DIV_ACLK_CORE_SHIFT) |		\
2408ab5aa876cb Jagan Teki 2022-09-15   91  	       HIWORD_UPDATE(_pclk_dbg, RV1126_DIV_PCLK_DBG_MASK,	\
2408ab5aa876cb Jagan Teki 2022-09-15   92  			     RV1126_DIV_PCLK_DBG_SHIFT),		\
2408ab5aa876cb Jagan Teki 2022-09-15   93  }
2408ab5aa876cb Jagan Teki 2022-09-15   94  
2408ab5aa876cb Jagan Teki 2022-09-15   95  #define RV1126_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg)		\
2408ab5aa876cb Jagan Teki 2022-09-15   96  {									\
2408ab5aa876cb Jagan Teki 2022-09-15   97  	.prate = _prate,						\
2408ab5aa876cb Jagan Teki 2022-09-15   98  	.divs = {							\
2408ab5aa876cb Jagan Teki 2022-09-15   99  		RV1126_CLKSEL1(_aclk_core, _pclk_dbg),			\
2408ab5aa876cb Jagan Teki 2022-09-15  100  	},								\
2408ab5aa876cb Jagan Teki 2022-09-15  101  }
2408ab5aa876cb Jagan Teki 2022-09-15  102  
2408ab5aa876cb Jagan Teki 2022-09-15  103  static struct rockchip_cpuclk_rate_table rv1126_cpuclk_rates[] __initdata = {
2408ab5aa876cb Jagan Teki 2022-09-15  104  	RV1126_CPUCLK_RATE(1608000000, 1, 7),
2408ab5aa876cb Jagan Teki 2022-09-15  105  	RV1126_CPUCLK_RATE(1584000000, 1, 7),
2408ab5aa876cb Jagan Teki 2022-09-15  106  	RV1126_CPUCLK_RATE(1560000000, 1, 7),
2408ab5aa876cb Jagan Teki 2022-09-15  107  	RV1126_CPUCLK_RATE(1536000000, 1, 7),
2408ab5aa876cb Jagan Teki 2022-09-15  108  	RV1126_CPUCLK_RATE(1512000000, 1, 7),
2408ab5aa876cb Jagan Teki 2022-09-15  109  	RV1126_CPUCLK_RATE(1488000000, 1, 5),
2408ab5aa876cb Jagan Teki 2022-09-15  110  	RV1126_CPUCLK_RATE(1464000000, 1, 5),
2408ab5aa876cb Jagan Teki 2022-09-15  111  	RV1126_CPUCLK_RATE(1440000000, 1, 5),
2408ab5aa876cb Jagan Teki 2022-09-15  112  	RV1126_CPUCLK_RATE(1416000000, 1, 5),
2408ab5aa876cb Jagan Teki 2022-09-15  113  	RV1126_CPUCLK_RATE(1392000000, 1, 5),
2408ab5aa876cb Jagan Teki 2022-09-15  114  	RV1126_CPUCLK_RATE(1368000000, 1, 5),
2408ab5aa876cb Jagan Teki 2022-09-15  115  	RV1126_CPUCLK_RATE(1344000000, 1, 5),
2408ab5aa876cb Jagan Teki 2022-09-15  116  	RV1126_CPUCLK_RATE(1320000000, 1, 5),
2408ab5aa876cb Jagan Teki 2022-09-15  117  	RV1126_CPUCLK_RATE(1296000000, 1, 5),
2408ab5aa876cb Jagan Teki 2022-09-15  118  	RV1126_CPUCLK_RATE(1272000000, 1, 5),
2408ab5aa876cb Jagan Teki 2022-09-15  119  	RV1126_CPUCLK_RATE(1248000000, 1, 5),
2408ab5aa876cb Jagan Teki 2022-09-15  120  	RV1126_CPUCLK_RATE(1224000000, 1, 5),
2408ab5aa876cb Jagan Teki 2022-09-15  121  	RV1126_CPUCLK_RATE(1200000000, 1, 5),
2408ab5aa876cb Jagan Teki 2022-09-15  122  	RV1126_CPUCLK_RATE(1104000000, 1, 5),
2408ab5aa876cb Jagan Teki 2022-09-15  123  	RV1126_CPUCLK_RATE(1008000000, 1, 5),
2408ab5aa876cb Jagan Teki 2022-09-15  124  	RV1126_CPUCLK_RATE(912000000, 1, 5),
2408ab5aa876cb Jagan Teki 2022-09-15  125  	RV1126_CPUCLK_RATE(816000000, 1, 3),
2408ab5aa876cb Jagan Teki 2022-09-15  126  	RV1126_CPUCLK_RATE(696000000, 1, 3),
2408ab5aa876cb Jagan Teki 2022-09-15  127  	RV1126_CPUCLK_RATE(600000000, 1, 3),
2408ab5aa876cb Jagan Teki 2022-09-15  128  	RV1126_CPUCLK_RATE(408000000, 1, 1),
2408ab5aa876cb Jagan Teki 2022-09-15  129  	RV1126_CPUCLK_RATE(312000000, 1, 1),
2408ab5aa876cb Jagan Teki 2022-09-15  130  	RV1126_CPUCLK_RATE(216000000,  1, 1),
2408ab5aa876cb Jagan Teki 2022-09-15  131  	RV1126_CPUCLK_RATE(96000000, 1, 1),
2408ab5aa876cb Jagan Teki 2022-09-15  132  };
2408ab5aa876cb Jagan Teki 2022-09-15  133  
2408ab5aa876cb Jagan Teki 2022-09-15  134  static const struct rockchip_cpuclk_reg_data rv1126_cpuclk_data = {
2408ab5aa876cb Jagan Teki 2022-09-15  135  	.core_reg[0] = RV1126_CLKSEL_CON(0),
2408ab5aa876cb Jagan Teki 2022-09-15  136  	.div_core_shift[0] = 0,
2408ab5aa876cb Jagan Teki 2022-09-15  137  	.div_core_mask[0] = 0x1f,
2408ab5aa876cb Jagan Teki 2022-09-15  138  	.num_cores = 1,
2408ab5aa876cb Jagan Teki 2022-09-15  139  	.mux_core_alt = 0,
2408ab5aa876cb Jagan Teki 2022-09-15  140  	.mux_core_main = 2,
2408ab5aa876cb Jagan Teki 2022-09-15  141  	.mux_core_shift = 6,
2408ab5aa876cb Jagan Teki 2022-09-15  142  	.mux_core_mask = 0x3,
2408ab5aa876cb Jagan Teki 2022-09-15  143  };
2408ab5aa876cb Jagan Teki 2022-09-15  144  
2408ab5aa876cb Jagan Teki 2022-09-15  145  PNAME(mux_pll_p)			= { "xin24m" };
2408ab5aa876cb Jagan Teki 2022-09-15  146  PNAME(mux_rtc32k_p)			= { "clk_pmupvtm_divout", "xin32k", "clk_osc0_div32k" };
2408ab5aa876cb Jagan Teki 2022-09-15  147  PNAME(mux_wifi_p)			= { "clk_wifi_osc0", "clk_wifi_div" };
2408ab5aa876cb Jagan Teki 2022-09-15  148  PNAME(mux_gpll_usb480m_cpll_xin24m_p)	= { "gpll", "usb480m", "cpll", "xin24m" };
2408ab5aa876cb Jagan Teki 2022-09-15  149  PNAME(mux_uart1_p)			= { "sclk_uart1_div", "sclk_uart1_fracdiv", "xin24m" };
2408ab5aa876cb Jagan Teki 2022-09-15  150  PNAME(mux_xin24m_gpll_p)		= { "xin24m", "gpll" };
2408ab5aa876cb Jagan Teki 2022-09-15  151  PNAME(mux_gpll_xin24m_p)		= { "gpll", "xin24m" };
2408ab5aa876cb Jagan Teki 2022-09-15  152  PNAME(mux_xin24m_32k_p)			= { "xin24m", "clk_rtc32k" };
2408ab5aa876cb Jagan Teki 2022-09-15  153  PNAME(mux_usbphy_otg_ref_p)		= { "clk_ref12m", "xin_osc0_div2_usbphyref_otg" };
2408ab5aa876cb Jagan Teki 2022-09-15  154  PNAME(mux_usbphy_host_ref_p)		= { "clk_ref12m", "xin_osc0_div2_usbphyref_host" };
2408ab5aa876cb Jagan Teki 2022-09-15  155  PNAME(mux_mipidsiphy_ref_p)		= { "clk_ref24m", "xin_osc0_mipiphyref" };
2408ab5aa876cb Jagan Teki 2022-09-15  156  PNAME(mux_usb480m_p)			= { "xin24m", "usb480m_phy", "clk_rtc32k" };
2408ab5aa876cb Jagan Teki 2022-09-15 @157  PNAME(mux_armclk_p)			= { "gpll", "cpll", "apll" };
2408ab5aa876cb Jagan Teki 2022-09-15  158  PNAME(mux_gpll_cpll_dpll_p)		= { "gpll", "cpll", "dummy_dpll" };
2408ab5aa876cb Jagan Teki 2022-09-15  159  PNAME(mux_gpll_cpll_p)			= { "gpll", "cpll" };
2408ab5aa876cb Jagan Teki 2022-09-15  160  PNAME(mux_hclk_pclk_pdbus_p)		= { "gpll", "dummy_cpll" };
2408ab5aa876cb Jagan Teki 2022-09-15  161  PNAME(mux_gpll_cpll_usb480m_xin24m_p)	= { "gpll", "cpll", "usb480m", "xin24m" };
2408ab5aa876cb Jagan Teki 2022-09-15  162  PNAME(mux_uart0_p)			= { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
2408ab5aa876cb Jagan Teki 2022-09-15  163  PNAME(mux_uart2_p)			= { "sclk_uart2_div", "sclk_uart2_frac", "xin24m" };
2408ab5aa876cb Jagan Teki 2022-09-15  164  PNAME(mux_uart3_p)			= { "sclk_uart3_div", "sclk_uart3_frac", "xin24m" };
2408ab5aa876cb Jagan Teki 2022-09-15  165  PNAME(mux_uart4_p)			= { "sclk_uart4_div", "sclk_uart4_frac", "xin24m" };
2408ab5aa876cb Jagan Teki 2022-09-15  166  PNAME(mux_uart5_p)			= { "sclk_uart5_div", "sclk_uart5_frac", "xin24m" };
2408ab5aa876cb Jagan Teki 2022-09-15  167  PNAME(mux_cpll_gpll_p)			= { "cpll", "gpll" };
2408ab5aa876cb Jagan Teki 2022-09-15  168  PNAME(mux_i2s0_tx_p)			= { "mclk_i2s0_tx_div", "mclk_i2s0_tx_fracdiv", "i2s0_mclkin", "xin12m" };
2408ab5aa876cb Jagan Teki 2022-09-15  169  PNAME(mux_i2s0_rx_p)			= { "mclk_i2s0_rx_div", "mclk_i2s0_rx_fracdiv", "i2s0_mclkin", "xin12m" };
2408ab5aa876cb Jagan Teki 2022-09-15  170  PNAME(mux_i2s0_tx_out2io_p)		= { "mclk_i2s0_tx", "xin12m" };
2408ab5aa876cb Jagan Teki 2022-09-15  171  PNAME(mux_i2s0_rx_out2io_p)		= { "mclk_i2s0_rx", "xin12m" };
2408ab5aa876cb Jagan Teki 2022-09-15  172  PNAME(mux_i2s1_p)			= { "mclk_i2s1_div", "mclk_i2s1_fracdiv", "i2s1_mclkin", "xin12m" };
2408ab5aa876cb Jagan Teki 2022-09-15  173  PNAME(mux_i2s1_out2io_p)		= { "mclk_i2s1", "xin12m" };
2408ab5aa876cb Jagan Teki 2022-09-15  174  PNAME(mux_i2s2_p)			= { "mclk_i2s2_div", "mclk_i2s2_fracdiv", "i2s2_mclkin", "xin12m" };
2408ab5aa876cb Jagan Teki 2022-09-15  175  PNAME(mux_i2s2_out2io_p)		= { "mclk_i2s2", "xin12m" };
2408ab5aa876cb Jagan Teki 2022-09-15  176  PNAME(mux_gpll_cpll_xin24m_p)		= { "gpll", "cpll", "xin24m" };
2408ab5aa876cb Jagan Teki 2022-09-15  177  PNAME(mux_audpwm_p)			= { "sclk_audpwm_div", "sclk_audpwm_fracdiv", "xin24m" };
5c7a71fd82350c Jagan Teki 2023-07-31  178  PNAME(mux_dclk_vop_p)			= { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" };
2408ab5aa876cb Jagan Teki 2022-09-15  179  PNAME(mux_usb480m_gpll_p)		= { "usb480m", "gpll" };
2408ab5aa876cb Jagan Teki 2022-09-15  180  PNAME(clk_gmac_src_m0_p)		= { "clk_gmac_div", "clk_gmac_rgmii_m0" };
2408ab5aa876cb Jagan Teki 2022-09-15  181  PNAME(clk_gmac_src_m1_p)		= { "clk_gmac_div", "clk_gmac_rgmii_m1" };
2408ab5aa876cb Jagan Teki 2022-09-15  182  PNAME(mux_clk_gmac_src_p)		= { "clk_gmac_src_m0", "clk_gmac_src_m1" };
2408ab5aa876cb Jagan Teki 2022-09-15  183  PNAME(mux_rgmii_clk_p)			= { "clk_gmac_tx_div50", "clk_gmac_tx_div5", "clk_gmac_tx_src", "clk_gmac_tx_src"};
2408ab5aa876cb Jagan Teki 2022-09-15  184  PNAME(mux_rmii_clk_p)			= { "clk_gmac_rx_div20", "clk_gmac_rx_div2" };
2408ab5aa876cb Jagan Teki 2022-09-15  185  PNAME(mux_gmac_tx_rx_p)			= { "rgmii_mode_clk", "rmii_mode_clk" };
2408ab5aa876cb Jagan Teki 2022-09-15  186  PNAME(mux_dpll_gpll_p)			= { "dpll", "gpll" };
2408ab5aa876cb Jagan Teki 2022-09-15  187
kernel test robot Sept. 18, 2023, 5:07 p.m. UTC | #2 
Hi Elaine,

kernel test robot noticed the following build warnings:

[auto build test WARNING on rockchip/for-next]
[also build test WARNING on clk/clk-next linus/master v6.6-rc2 next-20230918]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Elaine-Zhang/clk-clk-fractional-divider-Export-clk_fractional_divider_general_approximation-API/20230918-154652
base:   https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next
patch link:    https://lore.kernel.org/r/20230918073151.7660-5-zhangqing%40rock-chips.com
patch subject: [PATCH v1 4/8] clk: rockchip: Avoid __clk_lookup() calls
config: arm64-defconfig (https://download.01.org/0day-ci/archive/20230919/202309190032.1NPAySNx-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230919/202309190032.1NPAySNx-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202309190032.1NPAySNx-lkp@intel.com/

All warnings (new ones prefixed by >>):

   In file included from drivers/clk/rockchip/clk-rk3328.c:13:
>> drivers/clk/rockchip/clk-rk3328.c:160:7: warning: 'mux_armclk_p' defined but not used [-Wunused-const-variable=]
     160 | PNAME(mux_armclk_p)             = { "apll_core",
         |       ^~~~~~~~~~~~
   drivers/clk/rockchip/clk.h:512:43: note: in definition of macro 'PNAME'
     512 | #define PNAME(x) static const char *const x[] __initconst
         |                                           ^
--
   In file included from drivers/clk/rockchip/clk-rk3588.c:13:
>> drivers/clk/rockchip/clk-rk3588.c:447:7: warning: 'mux_armclkb23_p' defined but not used [-Wunused-const-variable=]
     447 | PNAME(mux_armclkb23_p)                  = { "xin24m", "gpll", "b1pll",};
         |       ^~~~~~~~~~~~~~~
   drivers/clk/rockchip/clk.h:512:43: note: in definition of macro 'PNAME'
     512 | #define PNAME(x) static const char *const x[] __initconst
         |                                           ^
>> drivers/clk/rockchip/clk-rk3588.c:446:7: warning: 'mux_armclkb01_p' defined but not used [-Wunused-const-variable=]
     446 | PNAME(mux_armclkb01_p)                  = { "xin24m", "gpll", "b0pll",};
         |       ^~~~~~~~~~~~~~~
   drivers/clk/rockchip/clk.h:512:43: note: in definition of macro 'PNAME'
     512 | #define PNAME(x) static const char *const x[] __initconst
         |                                           ^
>> drivers/clk/rockchip/clk-rk3588.c:445:7: warning: 'mux_armclkl_p' defined but not used [-Wunused-const-variable=]
     445 | PNAME(mux_armclkl_p)                    = { "xin24m", "gpll", "lpll" };
         |       ^~~~~~~~~~~~~
   drivers/clk/rockchip/clk.h:512:43: note: in definition of macro 'PNAME'
     512 | #define PNAME(x) static const char *const x[] __initconst
         |                                           ^


vim +/mux_armclk_p +160 drivers/clk/rockchip/clk-rk3328.c

fe3511ad8a1cf6 Elaine Zhang 2016-12-29  144  
fe3511ad8a1cf6 Elaine Zhang 2016-12-29  145  PNAME(mux_2plls_p)		= { "cpll", "gpll" };
fe3511ad8a1cf6 Elaine Zhang 2016-12-29  146  PNAME(mux_gpll_cpll_p)		= { "gpll", "cpll" };
fe3511ad8a1cf6 Elaine Zhang 2016-12-29  147  PNAME(mux_cpll_gpll_apll_p)	= { "cpll", "gpll", "apll" };
fe3511ad8a1cf6 Elaine Zhang 2016-12-29  148  PNAME(mux_2plls_xin24m_p)	= { "cpll", "gpll", "xin24m" };
fe3511ad8a1cf6 Elaine Zhang 2016-12-29  149  PNAME(mux_2plls_hdmiphy_p)	= { "cpll", "gpll",
fe3511ad8a1cf6 Elaine Zhang 2016-12-29  150  				    "dummy_hdmiphy" };
fe3511ad8a1cf6 Elaine Zhang 2016-12-29  151  PNAME(mux_4plls_p)		= { "cpll", "gpll",
fe3511ad8a1cf6 Elaine Zhang 2016-12-29  152  				    "dummy_hdmiphy",
fe3511ad8a1cf6 Elaine Zhang 2016-12-29  153  				    "usb480m" };
fe3511ad8a1cf6 Elaine Zhang 2016-12-29  154  PNAME(mux_2plls_u480m_p)	= { "cpll", "gpll",
fe3511ad8a1cf6 Elaine Zhang 2016-12-29  155  				    "usb480m" };
fe3511ad8a1cf6 Elaine Zhang 2016-12-29  156  PNAME(mux_2plls_24m_u480m_p)	= { "cpll", "gpll",
fe3511ad8a1cf6 Elaine Zhang 2016-12-29  157  				     "xin24m", "usb480m" };
fe3511ad8a1cf6 Elaine Zhang 2016-12-29  158  
fe3511ad8a1cf6 Elaine Zhang 2016-12-29  159  PNAME(mux_ddrphy_p)		= { "dpll", "apll", "cpll" };
fe3511ad8a1cf6 Elaine Zhang 2016-12-29 @160  PNAME(mux_armclk_p)		= { "apll_core",
fe3511ad8a1cf6 Elaine Zhang 2016-12-29  161  				    "gpll_core",
fe3511ad8a1cf6 Elaine Zhang 2016-12-29  162  				    "dpll_core",
fe3511ad8a1cf6 Elaine Zhang 2016-12-29  163  				    "npll_core"};
fe3511ad8a1cf6 Elaine Zhang 2016-12-29  164  PNAME(mux_hdmiphy_p)		= { "hdmi_phy", "xin24m" };
fe3511ad8a1cf6 Elaine Zhang 2016-12-29  165  PNAME(mux_usb480m_p)		= { "usb480m_phy",
fe3511ad8a1cf6 Elaine Zhang 2016-12-29  166  				    "xin24m" };
fe3511ad8a1cf6 Elaine Zhang 2016-12-29  167
diff mbox series

Patch

diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index 6ea7fba9f9e5..9429d4f1fe41 100644
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -298,7 +298,8 @@  static int rockchip_cpuclk_notifier_cb(struct notifier_block *nb,
 }
 
 struct clk *rockchip_clk_register_cpuclk(const char *name,
-			const char *const *parent_names, u8 num_parents,
+			u8 num_parents,
+			struct clk *parent, struct clk *alt_parent,
 			const struct rockchip_cpuclk_reg_data *reg_data,
 			const struct rockchip_cpuclk_rate_table *rates,
 			int nrates, void __iomem *reg_base, spinlock_t *lock)
@@ -306,6 +307,7 @@  struct clk *rockchip_clk_register_cpuclk(const char *name,
 	struct rockchip_cpuclk *cpuclk;
 	struct clk_init_data init;
 	struct clk *clk, *cclk;
+	const char *parent_name;
 	int ret;
 
 	if (num_parents < 2) {
@@ -313,12 +315,18 @@  struct clk *rockchip_clk_register_cpuclk(const char *name,
 		return ERR_PTR(-EINVAL);
 	}
 
+	if (IS_ERR(parent) || IS_ERR(alt_parent)) {
+		pr_err("%s: invalid parent clock(s)\n", __func__);
+		return ERR_PTR(-EINVAL);
+	}
+
 	cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
 	if (!cpuclk)
 		return ERR_PTR(-ENOMEM);
 
+	parent_name = clk_hw_get_name(__clk_get_hw(parent));
 	init.name = name;
-	init.parent_names = &parent_names[reg_data->mux_core_main];
+	init.parent_names = &parent_name;
 	init.num_parents = 1;
 	init.ops = &rockchip_cpuclk_ops;
 
@@ -336,7 +344,7 @@  struct clk *rockchip_clk_register_cpuclk(const char *name,
 	cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb;
 	cpuclk->hw.init = &init;
 
-	cpuclk->alt_parent = __clk_lookup(parent_names[reg_data->mux_core_alt]);
+	cpuclk->alt_parent = alt_parent;
 	if (!cpuclk->alt_parent) {
 		pr_err("%s: could not lookup alternate parent: (%d)\n",
 		       __func__, reg_data->mux_core_alt);
@@ -351,11 +359,11 @@  struct clk *rockchip_clk_register_cpuclk(const char *name,
 		goto free_cpuclk;
 	}
 
-	clk = __clk_lookup(parent_names[reg_data->mux_core_main]);
+	clk = parent;
 	if (!clk) {
 		pr_err("%s: could not lookup parent clock: (%d) %s\n",
 		       __func__, reg_data->mux_core_main,
-		       parent_names[reg_data->mux_core_main]);
+		       parent_name);
 		ret = -EINVAL;
 		goto free_alt_parent;
 	}
diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c
index 02fdb6273f4a..011b8bd89253 100644
--- a/drivers/clk/rockchip/clk-px30.c
+++ b/drivers/clk/rockchip/clk-px30.c
@@ -136,7 +136,6 @@  static const struct rockchip_cpuclk_reg_data px30_cpuclk_data = {
 
 PNAME(mux_pll_p)		= { "xin24m"};
 PNAME(mux_usb480m_p)		= { "xin24m", "usb480m_phy", "clk_rtc32k_pmu" };
-PNAME(mux_armclk_p)		= { "apll_core", "gpll_core" };
 PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_ddr" };
 PNAME(mux_ddrstdby_p)		= { "clk_ddrphy1x", "clk_stdby_2wrap" };
 PNAME(mux_4plls_p)		= { "gpll", "dummy_cpll", "usb480m", "npll" };
@@ -979,6 +978,7 @@  static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = {
 	GATE(0, "pclk_cru_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 8, GFLAGS),
 };
 
+static struct rockchip_clk_provider *cru_ctx;
 static void __init px30_clk_init(struct device_node *np)
 {
 	struct rockchip_clk_provider *ctx;
@@ -1003,17 +1003,14 @@  static void __init px30_clk_init(struct device_node *np)
 	rockchip_clk_register_branches(ctx, px30_clk_branches,
 				       ARRAY_SIZE(px30_clk_branches));
 
-	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
-				     mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
-				     &px30_cpuclk_data, px30_cpuclk_rates,
-				     ARRAY_SIZE(px30_cpuclk_rates));
-
 	rockchip_register_softrst(np, 12, reg_base + PX30_SOFTRST_CON(0),
 				  ROCKCHIP_SOFTRST_HIWORD_MASK);
 
 	rockchip_register_restart_notifier(ctx, PX30_GLB_SRST_FST, NULL);
 
 	rockchip_clk_of_add_provider(np, ctx);
+
+	cru_ctx = ctx;
 }
 CLK_OF_DECLARE(px30_cru, "rockchip,px30-cru", px30_clk_init);
 
@@ -1021,6 +1018,7 @@  static void __init px30_pmu_clk_init(struct device_node *np)
 {
 	struct rockchip_clk_provider *ctx;
 	void __iomem *reg_base;
+	struct clk **pmucru_clks, **cru_clks;
 
 	reg_base = of_iomap(np, 0);
 	if (!reg_base) {
@@ -1033,10 +1031,17 @@  static void __init px30_pmu_clk_init(struct device_node *np)
 		pr_err("%s: rockchip pmu clk init failed\n", __func__);
 		return;
 	}
+	pmucru_clks = ctx->clk_data.clks;
+	cru_clks = cru_ctx->clk_data.clks;
 
 	rockchip_clk_register_plls(ctx, px30_pmu_pll_clks,
 				   ARRAY_SIZE(px30_pmu_pll_clks), PX30_GRF_SOC_STATUS0);
 
+	rockchip_clk_register_armclk(cru_ctx, ARMCLK, "armclk",
+				     2, cru_clks[PLL_APLL], pmucru_clks[PLL_GPLL],
+				     &px30_cpuclk_data, px30_cpuclk_rates,
+				     ARRAY_SIZE(px30_cpuclk_rates));
+
 	rockchip_clk_register_branches(ctx, px30_clk_pmu_branches,
 				       ARRAY_SIZE(px30_clk_pmu_branches));
 
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index 7cba188d9b01..a0089c89f143 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -114,7 +114,6 @@  static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = {
 
 PNAME(mux_pll_p)		= { "xin24m", "xin24m" };
 
-PNAME(mux_armclk_p)		= { "apll", "gpll_armclk" };
 PNAME(mux_busclk_p)		= { "apll", "dpll_cpu", "gpll_cpu" };
 PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_ddr" };
 PNAME(mux_pll_src_3plls_p)	= { "apll", "dpll", "gpll" };
@@ -431,6 +430,7 @@  static void __init rk3036_clk_init(struct device_node *np)
 	struct rockchip_clk_provider *ctx;
 	void __iomem *reg_base;
 	struct clk *clk;
+	struct clk **clks;
 
 	reg_base = of_iomap(np, 0);
 	if (!reg_base) {
@@ -451,6 +451,7 @@  static void __init rk3036_clk_init(struct device_node *np)
 		iounmap(reg_base);
 		return;
 	}
+	clks = ctx->clk_data.clks;
 
 	clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
 	if (IS_ERR(clk))
@@ -464,7 +465,7 @@  static void __init rk3036_clk_init(struct device_node *np)
 				  ARRAY_SIZE(rk3036_clk_branches));
 
 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
-			mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
+			2, clks[PLL_APLL], clks[PLL_GPLL],
 			&rk3036_cpuclk_data, rk3036_cpuclk_rates,
 			ARRAY_SIZE(rk3036_cpuclk_rates));
 
diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c
index 09931fc7dadc..f9c78b26f973 100644
--- a/drivers/clk/rockchip/clk-rk3128.c
+++ b/drivers/clk/rockchip/clk-rk3128.c
@@ -130,7 +130,6 @@  static const struct rockchip_cpuclk_reg_data rk3128_cpuclk_data = {
 PNAME(mux_pll_p)		= { "clk_24m", "xin24m" };
 
 PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_div2_ddr" };
-PNAME(mux_armclk_p)		= { "apll_core", "gpll_div2_core" };
 PNAME(mux_usb480m_p)		= { "usb480m_phy", "xin24m" };
 PNAME(mux_aclk_cpu_src_p)	= { "cpll", "gpll", "gpll_div2", "gpll_div3" };
 
@@ -566,6 +565,7 @@  static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device
 {
 	struct rockchip_clk_provider *ctx;
 	void __iomem *reg_base;
+	struct clk **clks;
 
 	reg_base = of_iomap(np, 0);
 	if (!reg_base) {
@@ -579,6 +579,7 @@  static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device
 		iounmap(reg_base);
 		return ERR_PTR(-ENOMEM);
 	}
+	clks = ctx->clk_data.clks;
 
 	rockchip_clk_register_plls(ctx, rk3128_pll_clks,
 				   ARRAY_SIZE(rk3128_pll_clks),
@@ -587,7 +588,7 @@  static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device
 				  ARRAY_SIZE(common_clk_branches));
 
 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
-			mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
+			2, clks[PLL_APLL], clks[PLL_GPLL_DIV2],
 			&rk3128_cpuclk_data, rk3128_cpuclk_rates,
 			ARRAY_SIZE(rk3128_cpuclk_rates));
 
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index 455245815a11..d905299e5f4b 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -196,7 +196,6 @@  static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = {
 };
 
 PNAME(mux_pll_p)		= { "xin24m", "xin32k" };
-PNAME(mux_armclk_p)		= { "apll", "gpll_armclk" };
 PNAME(mux_ddrphy_p)		= { "dpll", "gpll_ddr" };
 PNAME(mux_pll_src_gpll_cpll_p)	= { "gpll", "cpll" };
 PNAME(mux_pll_src_cpll_gpll_p)	= { "cpll", "gpll" };
@@ -678,7 +677,7 @@  static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
 			div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS),
 
 	/* do not source aclk_cpu_pre from the apll, to keep complexity down */
-	COMPOSITE_NOGATE(0, "aclk_cpu_pre", mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT,
+	COMPOSITE_NOGATE(ACLK_CPU_PRE, "aclk_cpu_pre", mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT,
 			RK2928_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS),
 	DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0,
 			RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
@@ -778,10 +777,12 @@  static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device
 static void __init rk3066a_clk_init(struct device_node *np)
 {
 	struct rockchip_clk_provider *ctx;
+	struct clk **clks;
 
 	ctx = rk3188_common_clk_init(np);
 	if (IS_ERR(ctx))
 		return;
+	clks = ctx->clk_data.clks;
 
 	rockchip_clk_register_plls(ctx, rk3066_pll_clks,
 				   ARRAY_SIZE(rk3066_pll_clks),
@@ -789,7 +790,7 @@  static void __init rk3066a_clk_init(struct device_node *np)
 	rockchip_clk_register_branches(ctx, rk3066a_clk_branches,
 				  ARRAY_SIZE(rk3066a_clk_branches));
 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
-			mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
+			2, clks[PLL_APLL], clks[PLL_GPLL],
 			&rk3066_cpuclk_data, rk3066_cpuclk_rates,
 			ARRAY_SIZE(rk3066_cpuclk_rates));
 	rockchip_clk_of_add_provider(np, ctx);
@@ -799,13 +800,14 @@  CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init);
 static void __init rk3188a_clk_init(struct device_node *np)
 {
 	struct rockchip_clk_provider *ctx;
-	struct clk *clk1, *clk2;
+	struct clk **clks;
 	unsigned long rate;
 	int ret;
 
 	ctx = rk3188_common_clk_init(np);
 	if (IS_ERR(ctx))
 		return;
+	clks = ctx->clk_data.clks;
 
 	rockchip_clk_register_plls(ctx, rk3188_pll_clks,
 				   ARRAY_SIZE(rk3188_pll_clks),
@@ -813,22 +815,20 @@  static void __init rk3188a_clk_init(struct device_node *np)
 	rockchip_clk_register_branches(ctx, rk3188_clk_branches,
 				  ARRAY_SIZE(rk3188_clk_branches));
 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
-				  mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
+				  2, clks[PLL_APLL], clks[PLL_GPLL],
 				  &rk3188_cpuclk_data, rk3188_cpuclk_rates,
 				  ARRAY_SIZE(rk3188_cpuclk_rates));
 
 	/* reparent aclk_cpu_pre from apll */
-	clk1 = __clk_lookup("aclk_cpu_pre");
-	clk2 = __clk_lookup("gpll");
-	if (clk1 && clk2) {
-		rate = clk_get_rate(clk1);
+	if (clks[ACLK_CPU_PRE] && clks[PLL_GPLL]) {
+		rate = clk_get_rate(clks[ACLK_CPU_PRE]);
 
-		ret = clk_set_parent(clk1, clk2);
+		ret = clk_set_parent(clks[ACLK_CPU_PRE], clks[PLL_GPLL]);
 		if (ret < 0)
 			pr_warn("%s: could not reparent aclk_cpu_pre to gpll\n",
 				__func__);
 
-		clk_set_rate(clk1, rate);
+		clk_set_rate(clks[ACLK_CPU_PRE], rate);
 	} else {
 		pr_warn("%s: missing clocks to reparent aclk_cpu_pre to gpll\n",
 			__func__);
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
index bcbf8f901965..6f185d65123a 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -132,7 +132,6 @@  static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = {
 PNAME(mux_pll_p)		= { "clk_24m", "xin24m" };
 
 PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_ddr", "apll_ddr" };
-PNAME(mux_armclk_p)		= { "apll_core", "gpll_core", "dpll_core" };
 PNAME(mux_usb480m_phy_p)	= { "usb480m_phy0", "usb480m_phy1" };
 PNAME(mux_usb480m_p)		= { "usb480m_phy", "xin24m" };
 PNAME(mux_hdmiphy_p)		= { "hdmiphy_phy", "xin24m" };
@@ -660,6 +659,7 @@  static void __init rk3228_clk_init(struct device_node *np)
 {
 	struct rockchip_clk_provider *ctx;
 	void __iomem *reg_base;
+	struct clk **clks;
 
 	reg_base = of_iomap(np, 0);
 	if (!reg_base) {
@@ -673,6 +673,7 @@  static void __init rk3228_clk_init(struct device_node *np)
 		iounmap(reg_base);
 		return;
 	}
+	clks = ctx->clk_data.clks;
 
 	rockchip_clk_register_plls(ctx, rk3228_pll_clks,
 				   ARRAY_SIZE(rk3228_pll_clks),
@@ -681,7 +682,7 @@  static void __init rk3228_clk_init(struct device_node *np)
 				  ARRAY_SIZE(rk3228_clk_branches));
 
 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
-			mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
+			3, clks[PLL_APLL], clks[PLL_GPLL],
 			&rk3228_cpuclk_data, rk3228_cpuclk_rates,
 			ARRAY_SIZE(rk3228_cpuclk_rates));
 
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 89db93c46403..81ab67716906 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -190,7 +190,6 @@  static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {
 };
 
 PNAME(mux_pll_p)		= { "xin24m", "xin32k" };
-PNAME(mux_armclk_p)		= { "apll_core", "gpll_core" };
 PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_ddr" };
 PNAME(mux_aclk_cpu_src_p)	= { "cpll_aclk_cpu", "gpll_aclk_cpu" };
 
@@ -922,6 +921,7 @@  static void __init rk3288_common_init(struct device_node *np,
 				      enum rk3288_variant soc)
 {
 	struct rockchip_clk_provider *ctx;
+	struct clk **clks;
 
 	rk3288_cru_base = of_iomap(np, 0);
 	if (!rk3288_cru_base) {
@@ -935,6 +935,7 @@  static void __init rk3288_common_init(struct device_node *np,
 		iounmap(rk3288_cru_base);
 		return;
 	}
+	clks = ctx->clk_data.clks;
 
 	rockchip_clk_register_plls(ctx, rk3288_pll_clks,
 				   ARRAY_SIZE(rk3288_pll_clks),
@@ -950,7 +951,7 @@  static void __init rk3288_common_init(struct device_node *np,
 					       ARRAY_SIZE(rk3288_hclkvio_branch));
 
 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
-			mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
+			2, clks[PLL_APLL], clks[PLL_GPLL],
 			&rk3288_cpuclk_data, rk3288_cpuclk_rates,
 			ARRAY_SIZE(rk3288_cpuclk_rates));
 
diff --git a/drivers/clk/rockchip/clk-rk3308.c b/drivers/clk/rockchip/clk-rk3308.c
index 16a4dbd74146..b02154767a4e 100644
--- a/drivers/clk/rockchip/clk-rk3308.c
+++ b/drivers/clk/rockchip/clk-rk3308.c
@@ -121,7 +121,6 @@  static const struct rockchip_cpuclk_reg_data rk3308_cpuclk_data = {
 
 PNAME(mux_pll_p)		= { "xin24m" };
 PNAME(mux_usb480m_p)		= { "xin24m", "usb480m_phy", "clk_rtc32k" };
-PNAME(mux_armclk_p)		= { "apll_core", "vpll0_core", "vpll1_core" };
 PNAME(mux_dpll_vpll0_p)		= { "dpll", "vpll0" };
 PNAME(mux_dpll_vpll0_xin24m_p)	= { "dpll", "vpll0", "xin24m" };
 PNAME(mux_dpll_vpll0_vpll1_p)	= { "dpll", "vpll0", "vpll1" };
@@ -905,6 +904,7 @@  static void __init rk3308_clk_init(struct device_node *np)
 {
 	struct rockchip_clk_provider *ctx;
 	void __iomem *reg_base;
+	struct clk **clks;
 
 	reg_base = of_iomap(np, 0);
 	if (!reg_base) {
@@ -918,6 +918,7 @@  static void __init rk3308_clk_init(struct device_node *np)
 		iounmap(reg_base);
 		return;
 	}
+	clks = ctx->clk_data.clks;
 
 	rockchip_clk_register_plls(ctx, rk3308_pll_clks,
 				   ARRAY_SIZE(rk3308_pll_clks),
@@ -926,7 +927,7 @@  static void __init rk3308_clk_init(struct device_node *np)
 				       ARRAY_SIZE(rk3308_clk_branches));
 
 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
-				     mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
+				     3, clks[PLL_APLL], clks[PLL_VPLL0],
 				     &rk3308_cpuclk_data, rk3308_cpuclk_rates,
 				     ARRAY_SIZE(rk3308_cpuclk_rates));
 
diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
index a8686db20f0a..e6f86e460640 100644
--- a/drivers/clk/rockchip/clk-rk3328.c
+++ b/drivers/clk/rockchip/clk-rk3328.c
@@ -840,6 +840,7 @@  static void __init rk3328_clk_init(struct device_node *np)
 {
 	struct rockchip_clk_provider *ctx;
 	void __iomem *reg_base;
+	struct clk **clks;
 
 	reg_base = of_iomap(np, 0);
 	if (!reg_base) {
@@ -853,6 +854,7 @@  static void __init rk3328_clk_init(struct device_node *np)
 		iounmap(reg_base);
 		return;
 	}
+	clks = ctx->clk_data.clks;
 
 	rockchip_clk_register_plls(ctx, rk3328_pll_clks,
 				   ARRAY_SIZE(rk3328_pll_clks),
@@ -861,7 +863,7 @@  static void __init rk3328_clk_init(struct device_node *np)
 				       ARRAY_SIZE(rk3328_clk_branches));
 
 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
-				     mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
+				     4, clks[PLL_APLL], clks[PLL_GPLL],
 				     &rk3328_cpuclk_data, rk3328_cpuclk_rates,
 				     ARRAY_SIZE(rk3328_cpuclk_rates));
 
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 3594454e3f45..17df0933c8cb 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -88,8 +88,6 @@  static struct rockchip_pll_rate_table rk3368_pll_rates[] = {
 };
 
 PNAME(mux_pll_p)		= { "xin24m", "xin32k" };
-PNAME(mux_armclkb_p)		= { "apllb_core", "gpllb_core" };
-PNAME(mux_armclkl_p)		= { "aplll_core", "gplll_core" };
 PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_ddr" };
 PNAME(mux_cs_src_p)		= { "apllb_cs", "aplll_cs", "gpll_cs"};
 PNAME(mux_aclk_bus_src_p)	= { "cpll_aclk_bus", "gpll_aclk_bus" };
@@ -856,6 +854,7 @@  static void __init rk3368_clk_init(struct device_node *np)
 {
 	struct rockchip_clk_provider *ctx;
 	void __iomem *reg_base;
+	struct clk **clks;
 
 	reg_base = of_iomap(np, 0);
 	if (!reg_base) {
@@ -869,6 +868,7 @@  static void __init rk3368_clk_init(struct device_node *np)
 		iounmap(reg_base);
 		return;
 	}
+	clks = ctx->clk_data.clks;
 
 	rockchip_clk_register_plls(ctx, rk3368_pll_clks,
 				   ARRAY_SIZE(rk3368_pll_clks),
@@ -877,12 +877,12 @@  static void __init rk3368_clk_init(struct device_node *np)
 				  ARRAY_SIZE(rk3368_clk_branches));
 
 	rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
-			mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
+			2, clks[PLL_APLLB], clks[PLL_GPLL],
 			&rk3368_cpuclkb_data, rk3368_cpuclkb_rates,
 			ARRAY_SIZE(rk3368_cpuclkb_rates));
 
 	rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
-			mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
+			2, clks[PLL_APLLL], clks[PLL_GPLL],
 			&rk3368_cpuclkl_data, rk3368_cpuclkl_rates,
 			ARRAY_SIZE(rk3368_cpuclkl_rates));
 
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 619950265e8d..ee3bda968574 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -108,14 +108,6 @@  static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
 /* CRU parents */
 PNAME(mux_pll_p)				= { "xin24m", "xin32k" };
 
-PNAME(mux_armclkl_p)				= { "clk_core_l_lpll_src",
-						    "clk_core_l_bpll_src",
-						    "clk_core_l_dpll_src",
-						    "clk_core_l_gpll_src" };
-PNAME(mux_armclkb_p)				= { "clk_core_b_lpll_src",
-						    "clk_core_b_bpll_src",
-						    "clk_core_b_dpll_src",
-						    "clk_core_b_gpll_src" };
 PNAME(mux_ddrclk_p)				= { "clk_ddrc_lpll_src",
 						    "clk_ddrc_bpll_src",
 						    "clk_ddrc_dpll_src",
@@ -1507,6 +1499,7 @@  static void __init rk3399_clk_init(struct device_node *np)
 {
 	struct rockchip_clk_provider *ctx;
 	void __iomem *reg_base;
+	struct clk **clks;
 
 	reg_base = of_iomap(np, 0);
 	if (!reg_base) {
@@ -1520,6 +1513,7 @@  static void __init rk3399_clk_init(struct device_node *np)
 		iounmap(reg_base);
 		return;
 	}
+	clks = ctx->clk_data.clks;
 
 	rockchip_clk_register_plls(ctx, rk3399_pll_clks,
 				   ARRAY_SIZE(rk3399_pll_clks), -1);
@@ -1528,12 +1522,12 @@  static void __init rk3399_clk_init(struct device_node *np)
 				  ARRAY_SIZE(rk3399_clk_branches));
 
 	rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
-			mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
+			4, clks[PLL_APLLL], clks[PLL_GPLL],
 			&rk3399_cpuclkl_data, rk3399_cpuclkl_rates,
 			ARRAY_SIZE(rk3399_cpuclkl_rates));
 
 	rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
-			mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
+			4, clks[PLL_APLLB], clks[PLL_GPLL],
 			&rk3399_cpuclkb_data, rk3399_cpuclkb_rates,
 			ARRAY_SIZE(rk3399_cpuclkb_rates));
 
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index b1d173ef7da3..64d2278825ab 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -211,7 +211,6 @@  static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = {
 
 PNAME(mux_pll_p)			= { "xin24m" };
 PNAME(mux_usb480m_p)			= { "xin24m", "usb480m_phy", "clk_rtc_32k" };
-PNAME(mux_armclk_p)			= { "apll", "gpll" };
 PNAME(clk_i2s0_8ch_tx_p)		= { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" };
 PNAME(clk_i2s0_8ch_rx_p)		= { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" };
 PNAME(clk_i2s1_8ch_tx_p)		= { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin_osc0_half" };
@@ -1616,6 +1615,7 @@  static void __init rk3568_clk_init(struct device_node *np)
 {
 	struct rockchip_clk_provider *ctx;
 	void __iomem *reg_base;
+	struct clk **clks;
 
 	reg_base = of_iomap(np, 0);
 	if (!reg_base) {
@@ -1629,13 +1629,14 @@  static void __init rk3568_clk_init(struct device_node *np)
 		iounmap(reg_base);
 		return;
 	}
+	clks = ctx->clk_data.clks;
 
 	rockchip_clk_register_plls(ctx, rk3568_pll_clks,
 				   ARRAY_SIZE(rk3568_pll_clks),
 				   RK3568_GRF_SOC_STATUS0);
 
 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
-				     mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
+				     2, clks[PLL_APLL], clks[PLL_GPLL],
 				     &rk3568_cpuclk_data, rk3568_cpuclk_rates,
 				     ARRAY_SIZE(rk3568_cpuclk_rates));
 
diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c
index 6994165e0395..6f0db8ce3ba9 100644
--- a/drivers/clk/rockchip/clk-rk3588.c
+++ b/drivers/clk/rockchip/clk-rk3588.c
@@ -2459,6 +2459,7 @@  static void __init rk3588_clk_init(struct device_node *np)
 {
 	struct rockchip_clk_provider *ctx;
 	void __iomem *reg_base;
+	struct clk **clks;
 
 	reg_base = of_iomap(np, 0);
 	if (!reg_base) {
@@ -2472,21 +2473,22 @@  static void __init rk3588_clk_init(struct device_node *np)
 		iounmap(reg_base);
 		return;
 	}
+	clks = ctx->clk_data.clks;
 
 	rockchip_clk_register_plls(ctx, rk3588_pll_clks,
 				   ARRAY_SIZE(rk3588_pll_clks),
 				   RK3588_GRF_SOC_STATUS0);
 
 	rockchip_clk_register_armclk(ctx, ARMCLK_L, "armclk_l",
-			mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
+			3, clks[PLL_LPLL], clks[PLL_GPLL],
 			&rk3588_cpulclk_data, rk3588_cpulclk_rates,
 			ARRAY_SIZE(rk3588_cpulclk_rates));
 	rockchip_clk_register_armclk(ctx, ARMCLK_B01, "armclk_b01",
-			mux_armclkb01_p, ARRAY_SIZE(mux_armclkb01_p),
+			3, clks[PLL_B0PLL], clks[PLL_GPLL],
 			&rk3588_cpub0clk_data, rk3588_cpub0clk_rates,
 			ARRAY_SIZE(rk3588_cpub0clk_rates));
 	rockchip_clk_register_armclk(ctx, ARMCLK_B23, "armclk_b23",
-			mux_armclkb23_p, ARRAY_SIZE(mux_armclkb23_p),
+			3, clks[PLL_B1PLL], clks[PLL_GPLL],
 			&rk3588_cpub1clk_data, rk3588_cpub1clk_rates,
 			ARRAY_SIZE(rk3588_cpub1clk_rates));
 
diff --git a/drivers/clk/rockchip/clk-rv1108.c b/drivers/clk/rockchip/clk-rv1108.c
index d290a4cf68b5..394eaf0198bb 100644
--- a/drivers/clk/rockchip/clk-rv1108.c
+++ b/drivers/clk/rockchip/clk-rv1108.c
@@ -118,7 +118,6 @@  static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = {
 
 PNAME(mux_pll_p)		= { "xin24m", "xin24m"};
 PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_ddr", "apll_ddr" };
-PNAME(mux_armclk_p)		= { "apll_core", "gpll_core", "dpll_core" };
 PNAME(mux_usb480m_pre_p)	= { "usbphy", "xin24m" };
 PNAME(mux_hdmiphy_phy_p)	= { "hdmiphy", "xin24m" };
 PNAME(mux_dclk_hdmiphy_pre_p)	= { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" };
@@ -772,6 +771,7 @@  static void __init rv1108_clk_init(struct device_node *np)
 {
 	struct rockchip_clk_provider *ctx;
 	void __iomem *reg_base;
+	struct clk **clks;
 
 	reg_base = of_iomap(np, 0);
 	if (!reg_base) {
@@ -785,6 +785,7 @@  static void __init rv1108_clk_init(struct device_node *np)
 		iounmap(reg_base);
 		return;
 	}
+	clks = ctx->clk_data.clks;
 
 	rockchip_clk_register_plls(ctx, rv1108_pll_clks,
 				   ARRAY_SIZE(rv1108_pll_clks),
@@ -793,7 +794,7 @@  static void __init rv1108_clk_init(struct device_node *np)
 				  ARRAY_SIZE(rv1108_clk_branches));
 
 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
-			mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
+			3, clks[PLL_APLL], clks[PLL_GPLL],
 			&rv1108_cpuclk_data, rv1108_cpuclk_rates,
 			ARRAY_SIZE(rv1108_cpuclk_rates));
 
diff --git a/drivers/clk/rockchip/clk-rv1126.c b/drivers/clk/rockchip/clk-rv1126.c
index 8eb0e2dfcb28..afd5c67cf244 100644
--- a/drivers/clk/rockchip/clk-rv1126.c
+++ b/drivers/clk/rockchip/clk-rv1126.c
@@ -1056,6 +1056,7 @@  static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
 			RV1126_CLKGATE_CON(23), 0, GFLAGS),
 };
 
+static struct rockchip_clk_provider *pmucru_ctx;
 static void __init rv1126_pmu_clk_init(struct device_node *np)
 {
 	struct rockchip_clk_provider *ctx;
@@ -1084,12 +1085,15 @@  static void __init rv1126_pmu_clk_init(struct device_node *np)
 				  ROCKCHIP_SOFTRST_HIWORD_MASK);
 
 	rockchip_clk_of_add_provider(np, ctx);
+
+	pmucru_ctx = ctx;
 }
 
 static void __init rv1126_clk_init(struct device_node *np)
 {
 	struct rockchip_clk_provider *ctx;
 	void __iomem *reg_base;
+	struct clk **cru_clks, **pmucru_clks;
 
 	reg_base = of_iomap(np, 0);
 	if (!reg_base) {
@@ -1103,13 +1107,15 @@  static void __init rv1126_clk_init(struct device_node *np)
 		iounmap(reg_base);
 		return;
 	}
+	cru_clks = ctx->clk_data.clks;
+	pmucru_clks = pmucru_ctx->clk_data.clks;
 
 	rockchip_clk_register_plls(ctx, rv1126_pll_clks,
 				   ARRAY_SIZE(rv1126_pll_clks),
 				   RV1126_GRF_SOC_STATUS0);
 
 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
-				     mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
+				     3, cru_clks[PLL_APLL], pmucru_clks[PLL_GPLL],
 				     &rv1126_cpuclk_data, rv1126_cpuclk_rates,
 				     ARRAY_SIZE(rv1126_cpuclk_rates));
 
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 9f23bd5ee22d..73b89dd3ca7d 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -575,15 +575,17 @@  EXPORT_SYMBOL_GPL(rockchip_clk_register_branches);
 
 void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
 				  unsigned int lookup_id,
-				  const char *name, const char *const *parent_names,
+				  const char *name,
 				  u8 num_parents,
+				  struct clk *parent, struct clk *alt_parent,
 				  const struct rockchip_cpuclk_reg_data *reg_data,
 				  const struct rockchip_cpuclk_rate_table *rates,
 				  int nrates)
 {
 	struct clk *clk;
 
-	clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents,
+	clk = rockchip_clk_register_cpuclk(name, num_parents,
+		parent, alt_parent,
 					   reg_data, rates, nrates,
 					   ctx->reg_base, &ctx->lock);
 	if (IS_ERR(clk)) {
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 4fd3036817f4..a9937fc5804a 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -473,7 +473,8 @@  struct rockchip_cpuclk_reg_data {
 };
 
 struct clk *rockchip_clk_register_cpuclk(const char *name,
-			const char *const *parent_names, u8 num_parents,
+			u8 num_parents,
+			struct clk *parent, struct clk *alt_parent,
 			const struct rockchip_cpuclk_reg_data *reg_data,
 			const struct rockchip_cpuclk_rate_table *rates,
 			int nrates, void __iomem *reg_base, spinlock_t *lock);
@@ -979,12 +980,14 @@  void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
 void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
 				struct rockchip_pll_clock *pll_list,
 				unsigned int nr_pll, int grf_lock_offset);
-void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
-			unsigned int lookup_id, const char *name,
-			const char *const *parent_names, u8 num_parents,
-			const struct rockchip_cpuclk_reg_data *reg_data,
-			const struct rockchip_cpuclk_rate_table *rates,
-			int nrates);
+void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
+					 unsigned int lookup_id,
+					 const char *name,
+					 u8 num_parents,
+					 struct clk *parent, struct clk *alt_parent,
+					 const struct rockchip_cpuclk_reg_data *reg_data,
+					 const struct rockchip_cpuclk_rate_table *rates,
+					 int nrates);
 void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
 					unsigned int reg, void (*cb)(void));