diff mbox series

ARM64: dts: rk3399: Add the missing L2 cache information This patch fixes the kernel warning "cacheinfo: Unable to detect cache hierarchy for CPU 0" for the rk3399.

Message ID 20230925170821.3238161-1-vincent.belpois@gmail.com (mailing list archive)
State New, archived
Headers show
Series ARM64: dts: rk3399: Add the missing L2 cache information This patch fixes the kernel warning "cacheinfo: Unable to detect cache hierarchy for CPU 0" for the rk3399. | expand

Commit Message

Vincent Belpois Sept. 25, 2023, 5:08 p.m. UTC 
Signed-off-by: Vincent Belpois <vincent.belpois@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 9da0b6d77c8d..4da39f3fa692 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -71,11 +71,16 @@  cpu_l0: cpu@0 {
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x0>;
 			enable-method = "psci";
+			next-level-cache = <&l2_0>;
 			capacity-dmips-mhz = <485>;
 			clocks = <&cru ARMCLKL>;
 			#cooling-cells = <2>; /* min followed by max */
 			dynamic-power-coefficient = <100>;
 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+		
+			l2_0: l2-cache {
+				compatible = "cache,arm,arch-cache";
+			};
 		};
 
 		cpu_l1: cpu@1 {
@@ -83,6 +88,7 @@  cpu_l1: cpu@1 {
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x1>;
 			enable-method = "psci";
+			next-level-cache = <&l2_0>;
 			capacity-dmips-mhz = <485>;
 			clocks = <&cru ARMCLKL>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -95,6 +101,7 @@  cpu_l2: cpu@2 {
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x2>;
 			enable-method = "psci";
+			next-level-cache = <&l2_0>;
 			capacity-dmips-mhz = <485>;
 			clocks = <&cru ARMCLKL>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -107,6 +114,7 @@  cpu_l3: cpu@3 {
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x3>;
 			enable-method = "psci";
+			next-level-cache = <&l2_0>;
 			capacity-dmips-mhz = <485>;
 			clocks = <&cru ARMCLKL>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -119,6 +127,7 @@  cpu_b0: cpu@100 {
 			compatible = "arm,cortex-a72";
 			reg = <0x0 0x100>;
 			enable-method = "psci";
+			next-level-cache = <&l2_1>;
 			capacity-dmips-mhz = <1024>;
 			clocks = <&cru ARMCLKB>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -130,6 +139,9 @@  thermal-idle {
 				duration-us = <10000>;
 				exit-latency-us = <500>;
 			};
+			l2_1: l2-cache {
+				compatible = "cache,arm,arch-cache";
+			};
 		};
 
 		cpu_b1: cpu@101 {
@@ -137,6 +149,7 @@  cpu_b1: cpu@101 {
 			compatible = "arm,cortex-a72";
 			reg = <0x0 0x101>;
 			enable-method = "psci";
+			next-level-cache = <&l2_1>;
 			capacity-dmips-mhz = <1024>;
 			clocks = <&cru ARMCLKB>;
 			#cooling-cells = <2>; /* min followed by max */