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Wed, 4 Oct 2023 12:37:31 +0200 (CEST) Received: from localhost (10.201.20.120) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 4 Oct 2023 12:37:31 +0200 From: Hugues Fruchet To: Ezequiel Garcia , Philipp Zabel , Andrzej Pietrasiewicz , Nicolas Dufresne , Sakari Ailus , Benjamin Gaignard , Laurent Pinchart , Daniel Almeida , Benjamin Mugnier , Heiko Stuebner , Mauro Carvalho Chehab , Hans Verkuil , , Maxime Coquelin , Alexandre Torgue , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: Hugues Fruchet , Marco Felsch , Adam Ford Subject: [RFC 4/6] media: hantro: add VP8 encode support for STM32MP25 VENC Date: Wed, 4 Oct 2023 12:37:18 +0200 Message-ID: <20231004103720.3540436-5-hugues.fruchet@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231004103720.3540436-1-hugues.fruchet@foss.st.com> References: <20231004103720.3540436-1-hugues.fruchet@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.20.120] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-04_02,2023-10-02_01,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231004_033744_911343_FDFB391C X-CRM114-Status: GOOD ( 13.50 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Add VP8 stateless support for STM32MP25 VENC video hardware encoder. Signed-off-by: Hugues Fruchet --- .../platform/verisilicon/stm32mp25_venc_hw.c | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/verisilicon/stm32mp25_venc_hw.c b/drivers/media/platform/verisilicon/stm32mp25_venc_hw.c index 0aac33afcadc..2176eccd1f79 100644 --- a/drivers/media/platform/verisilicon/stm32mp25_venc_hw.c +++ b/drivers/media/platform/verisilicon/stm32mp25_venc_hw.c @@ -87,6 +87,19 @@ static const struct hantro_fmt stm32mp25_venc_fmts[] = { .step_height = MB_DIM, }, }, + { + .fourcc = V4L2_PIX_FMT_VP8_FRAME, + .codec_mode = HANTRO_MODE_VP8_ENC, + .max_depth = 2, + .frmsize = { + .min_width = 96, + .max_width = 4080, + .step_width = MB_DIM, + .min_height = 96, + .max_height = 4080, + .step_height = MB_DIM, + }, + }, }; static irqreturn_t stm32mp25_venc_irq(int irq, void *dev_id) @@ -120,6 +133,13 @@ static const struct hantro_codec_ops stm32mp25_venc_codec_ops[] = { .reset = stm32mp25_venc_reset, .done = hantro_h1_jpeg_enc_done, }, + [HANTRO_MODE_VP8_ENC] = { + .run = hantro_h1_vp8_enc_run, + .reset = stm32mp25_venc_reset, + .init = hantro_vp8_enc_init, + .done = hantro_h1_vp8_enc_done, + .exit = hantro_vp8_enc_exit, + }, }; /* @@ -137,7 +157,7 @@ static const char * const stm32mp25_venc_clk_names[] = { const struct hantro_variant stm32mp25_venc_variant = { .enc_fmts = stm32mp25_venc_fmts, .num_enc_fmts = ARRAY_SIZE(stm32mp25_venc_fmts), - .codec = HANTRO_JPEG_ENCODER, + .codec = HANTRO_JPEG_ENCODER | HANTRO_VP8_ENCODER, .codec_ops = stm32mp25_venc_codec_ops, .irqs = stm32mp25_venc_irqs, .num_irqs = ARRAY_SIZE(stm32mp25_venc_irqs),