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Sat, 25 Nov 2023 11:05:53 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a208:d471:6d33:4b36:d85]) by smtp.gmail.com with ESMTPSA id j26-20020a62b61a000000b006cbb7e27091sm4810529pff.175.2023.11.25.11.05.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 11:05:52 -0800 (PST) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Jagan Teki Subject: [PATCH v2 08/10] arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 B-Key, E-Key Date: Sun, 26 Nov 2023 00:35:20 +0530 Message-Id: <20231125190522.87607-9-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231125190522.87607-1-jagan@edgeble.ai> References: <20231125190522.87607-1-jagan@edgeble.ai> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231125_110555_323668_07F2F567 X-CRM114-Status: GOOD ( 10.87 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Edgeble NCM6A-IO board has M.2 B-Key, E-Key via PCI3x2. Add support for it. Signed-off-by: Jagan Teki --- Changes for v2: - suffix '-regulator' - use proper node name - fix commit head - update comments .../dts/rockchip/rk3588-edgeble-neu6a-io.dtsi | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi index 088a10fe042c..130b240e0da8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi @@ -23,6 +23,19 @@ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { vin-supply = <&vcc_3v3_s3>; }; + vcc3v3_pcie3x2: vcc3v3-pcie3x2-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; /* PCIE_4G_PWEN */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x2_vcc3v3_en>; + regulator-name = "vcc3v3_pcie3x2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + vcc3v3_pcie3x4: vcc3v3-pcie3x4-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -74,6 +87,15 @@ &pcie30phy { status = "okay"; }; +/* B-Key and E-Key */ +&pcie3x2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x2_rst>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTn_M1_L */ + vpcie3v3-supply = <&vcc3v3_pcie3x2>; + status = "okay"; +}; + /* M-Key */ &pcie3x4 { pinctrl-names = "default"; @@ -91,6 +113,14 @@ pcie2_0_rst: pcie2-0-rst { }; pcie3 { + pcie3x2_rst: pcie3x2-rst { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3x2_vcc3v3_en: pcie3x2-vcc3v3-en { + rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + pcie3x4_rst: pcie3x4-rst { rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; };