From patchwork Wed Mar 27 13:41:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Emmanuel Gil Peyrot X-Patchwork-Id: 13606700 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7F1AFC54E67 for ; Wed, 27 Mar 2024 13:41:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=CthLMLoOrfGs6iBV07wRp2haCHGbpFTSb6khqD7u/DA=; b=ln4kXWsYCEloe1 1+vs8g82+5gqKN24F9GvymZlKHsJE1788GyEqJQ7RFicxpPsHzIrzIsGbnhbkNdQ5A5g8x2SGj+Az +X2mR/xCiM1InF/Ek5AbLSN6VNhe3tPl9V+DRwavrDE4o8+cq+OZSVscjRqTmOembLbVZPBfvrjd7 MsRtSkDbCRuSyZzPf6bALkAuQFovfa/Pq8KFXQvoMqe/t0JUID9/lisimXYbQDMFX0VZEqBSMf4RH +P9g2ZQyOuSznTBimw/izw20nqJ4o7ZNZOQizwIB7sKc98jd3qm6wCU9kEEMhh+lOiRuIbP104HHr PT+OqIM52zrcy32Ipy+A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rpTX8-00000009FYW-0Jh9; Wed, 27 Mar 2024 13:41:38 +0000 Received: from [2a01:e0a:828:c7c0:e2d5:5eff:fe2d:8e8] (helo=luna.linkmauve.fr) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rpTWt-00000009FQb-1BhV; Wed, 27 Mar 2024 13:41:25 +0000 Received: by luna.linkmauve.fr (Postfix, from userid 1000) id DCE50101AF3A; Wed, 27 Mar 2024 14:41:18 +0100 (CET) From: Emmanuel Gil Peyrot To: linux-kernel@vger.kernel.org Cc: Emmanuel Gil Peyrot , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Joerg Roedel , Will Deacon , Robin Murphy , Sebastian Reichel , Cristian Ciocaltea , Dragan Simic , Shreeya Patel , Chris Morgan , Andy Yan , Nicolas Frattaroli , linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev Subject: [PATCH v2 2/2] arm64: dts: rockchip: Add VEPU121 to rk3588 Date: Wed, 27 Mar 2024 14:41:12 +0100 Message-ID: <20240327134115.424846-3-linkmauve@linkmauve.fr> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240327134115.424846-1-linkmauve@linkmauve.fr> References: <20240327134115.424846-1-linkmauve@linkmauve.fr> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240327_064123_519201_A6CA8571 X-CRM114-Status: UNSURE ( 9.54 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The TRM (version 1.0 page 385) lists five VEPU121 cores, but only four interrupts are listed (on page 24), so I’ve only enabled four of them for now. Signed-off-by: Emmanuel Gil Peyrot Reviewed-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 80 +++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 87b83c87bd55..510ed3db9d01 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -2488,6 +2488,86 @@ gpio4: gpio@fec50000 { }; }; + jpeg_enc0: video-codec@fdba0000 { + compatible = "rockchip,rk3588-vepu121", "rockchip,rk3568-vepu"; + reg = <0x0 0xfdba0000 0x0 0x800>; + interrupts = ; + clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; + clock-names = "aclk", "hclk"; + iommus = <&jpeg_enc0_mmu>; + power-domains = <&power RK3588_PD_VDPU>; + }; + + jpeg_enc0_mmu: iommu@fdba0800 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdba0800 0x0 0x40>; + interrupts = ; + clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VDPU>; + #iommu-cells = <0>; + }; + + jpeg_enc1: video-codec@fdba4000 { + compatible = "rockchip,rk3588-vepu121", "rockchip,rk3568-vepu"; + reg = <0x0 0xfdba4000 0x0 0x800>; + interrupts = ; + clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; + clock-names = "aclk", "hclk"; + iommus = <&jpeg_enc1_mmu>; + power-domains = <&power RK3588_PD_VDPU>; + }; + + jpeg_enc1_mmu: iommu@fdba4800 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdba4800 0x0 0x40>; + interrupts = ; + clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VDPU>; + #iommu-cells = <0>; + }; + + jpeg_enc2: video-codec@fdba8000 { + compatible = "rockchip,rk3588-vepu121", "rockchip,rk3568-vepu"; + reg = <0x0 0xfdba8000 0x0 0x800>; + interrupts = ; + clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; + clock-names = "aclk", "hclk"; + iommus = <&jpeg_enc2_mmu>; + power-domains = <&power RK3588_PD_VDPU>; + }; + + jpeg_enc2_mmu: iommu@fdba8800 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdba8800 0x0 0x40>; + interrupts = ; + clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VDPU>; + #iommu-cells = <0>; + }; + + jpeg_enc3: video-codec@fdbac000 { + compatible = "rockchip,rk3588-vepu121", "rockchip,rk3568-vepu"; + reg = <0x0 0xfdbac000 0x0 0x800>; + interrupts = ; + clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; + clock-names = "aclk", "hclk"; + iommus = <&jpeg_enc3_mmu>; + power-domains = <&power RK3588_PD_VDPU>; + }; + + jpeg_enc3_mmu: iommu@fdbac800 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdbac800 0x0 0x40>; + interrupts = ; + clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VDPU>; + #iommu-cells = <0>; + }; + av1d: video-codec@fdc70000 { compatible = "rockchip,rk3588-av1-vpu"; reg = <0x0 0xfdc70000 0x0 0x800>;