| Message ID | 20240822194956.918527-3-detlev.casanova@collabora.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add CRU support for rk3576 SoC | expand |
Hello Detlev, On 2024-08-22 21:49, Detlev Casanova wrote: > From: Elaine Zhang <zhangqing@rock-chips.com> > > That PLL type is similar to the other rk3588 pll types but the actual > rate is twice the configured rate. > Therefore, the returned calculated rate must be multiplied by two. > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> > (cherry picked from commit c99648df60d3763723de9e443b862da44e8872fe) > Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Thanks for the patch. I had a rather detailed look at the patch, while focusing on having no regressions introduced, and I found none. So, please feel free to include: Acked-by: Dragan Simic <dsimic@manjaro.org> > --- > drivers/clk/rockchip/clk-pll.c | 6 +++++- > drivers/clk/rockchip/clk.h | 1 + > 2 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/rockchip/clk-pll.c > b/drivers/clk/rockchip/clk-pll.c > index 606ce5458f54..fe76756e592e 100644 > --- a/drivers/clk/rockchip/clk-pll.c > +++ b/drivers/clk/rockchip/clk-pll.c > @@ -914,7 +914,10 @@ static unsigned long > rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned > } > rate64 = rate64 >> cur.s; > > - return (unsigned long)rate64; > + if (pll->type == pll_rk3588_ddr) > + return (unsigned long)rate64 * 2; > + else > + return (unsigned long)rate64; > } > > static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll > *pll, > @@ -1167,6 +1170,7 @@ struct clk *rockchip_clk_register_pll(struct > rockchip_clk_provider *ctx, > break; > case pll_rk3588: > case pll_rk3588_core: > + case pll_rk3588_ddr: > if (!pll->rate_table) > init.ops = &rockchip_rk3588_pll_clk_norate_ops; > else > diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h > index fd3b476dedda..40fc0e4703c1 100644 > --- a/drivers/clk/rockchip/clk.h > +++ b/drivers/clk/rockchip/clk.h > @@ -287,6 +287,7 @@ enum rockchip_pll_type { > pll_rk3399, > pll_rk3588, > pll_rk3588_core, > + pll_rk3588_ddr, > }; > > #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 606ce5458f54..fe76756e592e 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -914,7 +914,10 @@ static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned } rate64 = rate64 >> cur.s; - return (unsigned long)rate64; + if (pll->type == pll_rk3588_ddr) + return (unsigned long)rate64 * 2; + else + return (unsigned long)rate64; } static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll, @@ -1167,6 +1170,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, break; case pll_rk3588: case pll_rk3588_core: + case pll_rk3588_ddr: if (!pll->rate_table) init.ops = &rockchip_rk3588_pll_clk_norate_ops; else diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index fd3b476dedda..40fc0e4703c1 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -287,6 +287,7 @@ enum rockchip_pll_type { pll_rk3399, pll_rk3588, pll_rk3588_core, + pll_rk3588_ddr, }; #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \