| Message ID | 20240901183221.240361-2-linux.amoon@gmail.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v5,1/6] PCI: rockchip: Simplify clock handling by using clk_bulk*() function | expand |
Hi, On Mon, 2 Sept 2024 at 00:03, Anand Moon <linux.amoon@gmail.com> wrote: > > Refactor the clock handling in the Rockchip PCIe driver, > introducing a more robust and efficient method for enabling and > disabling clocks using clk_bulk*() API. Using the clk_bulk APIs, > the clock handling for the core clocks becomes much simpler. > > Signed-off-by: Anand Moon <linux.amoon@gmail.com> Do you have any review comments on this series? Thanks -Anand > --- > v5: switch to use use devm_clk_bulk_get_all()? gets rid of hardcoding the > clock names in driver. > v4: use dev_err_probe for error patch. > v3: Fix typo in commit message, dropped reported by. > v2: Fix compilation error reported by Intel test robot. > --- > --- > drivers/pci/controller/pcie-rockchip.c | 65 +++----------------------- > drivers/pci/controller/pcie-rockchip.h | 7 ++- > 2 files changed, 10 insertions(+), 62 deletions(-) > > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c > index c07d7129f1c7..2777ef0cb599 100644 > --- a/drivers/pci/controller/pcie-rockchip.c > +++ b/drivers/pci/controller/pcie-rockchip.c > @@ -127,29 +127,9 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) > "failed to get ep GPIO\n"); > } > > - rockchip->aclk_pcie = devm_clk_get(dev, "aclk"); > - if (IS_ERR(rockchip->aclk_pcie)) { > - dev_err(dev, "aclk clock not found\n"); > - return PTR_ERR(rockchip->aclk_pcie); > - } > - > - rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf"); > - if (IS_ERR(rockchip->aclk_perf_pcie)) { > - dev_err(dev, "aclk_perf clock not found\n"); > - return PTR_ERR(rockchip->aclk_perf_pcie); > - } > - > - rockchip->hclk_pcie = devm_clk_get(dev, "hclk"); > - if (IS_ERR(rockchip->hclk_pcie)) { > - dev_err(dev, "hclk clock not found\n"); > - return PTR_ERR(rockchip->hclk_pcie); > - } > - > - rockchip->clk_pcie_pm = devm_clk_get(dev, "pm"); > - if (IS_ERR(rockchip->clk_pcie_pm)) { > - dev_err(dev, "pm clock not found\n"); > - return PTR_ERR(rockchip->clk_pcie_pm); > - } > + rockchip->num_clks = devm_clk_bulk_get_all(dev, &rockchip->clks); > + if (rockchip->num_clks < 0) > + return dev_err_probe(dev, err, "failed to get clocks\n"); > > return 0; > } > @@ -372,39 +352,11 @@ int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip) > struct device *dev = rockchip->dev; > int err; > > - err = clk_prepare_enable(rockchip->aclk_pcie); > - if (err) { > - dev_err(dev, "unable to enable aclk_pcie clock\n"); > - return err; > - } > - > - err = clk_prepare_enable(rockchip->aclk_perf_pcie); > - if (err) { > - dev_err(dev, "unable to enable aclk_perf_pcie clock\n"); > - goto err_aclk_perf_pcie; > - } > - > - err = clk_prepare_enable(rockchip->hclk_pcie); > - if (err) { > - dev_err(dev, "unable to enable hclk_pcie clock\n"); > - goto err_hclk_pcie; > - } > - > - err = clk_prepare_enable(rockchip->clk_pcie_pm); > - if (err) { > - dev_err(dev, "unable to enable clk_pcie_pm clock\n"); > - goto err_clk_pcie_pm; > - } > + err = clk_bulk_prepare_enable(rockchip->num_clks, rockchip->clks); > + if (err) > + return dev_err_probe(dev, err, "failed to enable clocks\n"); > > return 0; > - > -err_clk_pcie_pm: > - clk_disable_unprepare(rockchip->hclk_pcie); > -err_hclk_pcie: > - clk_disable_unprepare(rockchip->aclk_perf_pcie); > -err_aclk_perf_pcie: > - clk_disable_unprepare(rockchip->aclk_pcie); > - return err; > } > EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks); > > @@ -412,10 +364,7 @@ void rockchip_pcie_disable_clocks(void *data) > { > struct rockchip_pcie *rockchip = data; > > - clk_disable_unprepare(rockchip->clk_pcie_pm); > - clk_disable_unprepare(rockchip->hclk_pcie); > - clk_disable_unprepare(rockchip->aclk_perf_pcie); > - clk_disable_unprepare(rockchip->aclk_pcie); > + clk_bulk_disable_unprepare(rockchip->num_clks, rockchip->clks); > } > EXPORT_SYMBOL_GPL(rockchip_pcie_disable_clocks); > > diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h > index 6111de35f84c..bebab80c9553 100644 > --- a/drivers/pci/controller/pcie-rockchip.h > +++ b/drivers/pci/controller/pcie-rockchip.h > @@ -11,6 +11,7 @@ > #ifndef _PCIE_ROCKCHIP_H > #define _PCIE_ROCKCHIP_H > > +#include <linux/clk.h> > #include <linux/kernel.h> > #include <linux/pci.h> > #include <linux/pci-ecam.h> > @@ -299,10 +300,8 @@ struct rockchip_pcie { > struct reset_control *pm_rst; > struct reset_control *aclk_rst; > struct reset_control *pclk_rst; > - struct clk *aclk_pcie; > - struct clk *aclk_perf_pcie; > - struct clk *hclk_pcie; > - struct clk *clk_pcie_pm; > + struct clk_bulk_data *clks; > + int num_clks; > struct regulator *vpcie12v; /* 12V power supply */ > struct regulator *vpcie3v3; /* 3.3V power supply */ > struct regulator *vpcie1v8; /* 1.8V power supply */ > -- > 2.44.0 >
On Fri, Sep 27, 2024 at 01:47:44PM +0530, Anand Moon wrote: > On Mon, 2 Sept 2024 at 00:03, Anand Moon <linux.amoon@gmail.com> wrote: > > > > Refactor the clock handling in the Rockchip PCIe driver, > > introducing a more robust and efficient method for enabling and > > disabling clocks using clk_bulk*() API. Using the clk_bulk APIs, > > the clock handling for the core clocks becomes much simpler. > > > > Signed-off-by: Anand Moon <linux.amoon@gmail.com> > > Do you have any review comments on this series? Looks like nice work, thanks. Minor tips below. We'll start applying PCI patches to v6.13-rc1 after it is tagged. It looks like these will apply cleanly, so no rebasing needed. - It would be helpful if you can add a cover letter (0/n), which is a good place for the overall diffstat and series-level changelog. - This v5 series adds drivers/phy patches, which are also related to rockchip, but will be handled by a different maintainer, so best to send them as separate series (and of course send the phy patches to the right maintainer, linux-phy, etc). - "b4 am -o/tmp/ 20240901183221.240361-2-linux.amoon@gmail.com" complains about something, I dunno how to fix: Checking attestation on all messages, may take a moment... --- ✗ [PATCH v5 1/6] PCI: rockchip: Simplify clock handling by using clk_bulk*() function ✗ [PATCH v5 2/6] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function ✗ [PATCH v5 3/6] PCI: rockchip: Refactor rockchip_pcie_disable_clocks function signature ✗ [PATCH v5 4/6] phy: rockchip-pcie: Simplify error handling with dev_err_probe() ✗ [PATCH v5 5/6] phy: rockchip-pcie: Change to use devm_clk_get_enabled() helper ✗ [PATCH v5 6/6] phy: rockchip-pcie: Use regmap_read_poll_timeout for PCIe reference clk PLL status --- ✗ BADSIG: DKIM/gmail.com - In 3/6 and 6/6 commit logs, add parens after function names as you did elsewhere. - Super nit: In 5/6, s/Change to use/Use/. Every patch is a change, so "Change to" doesn't add any information. Bjorn
Hi Bjorn, Thanks for your review comments. On Fri, 27 Sept 2024 at 23:52, Bjorn Helgaas <helgaas@kernel.org> wrote: > > On Fri, Sep 27, 2024 at 01:47:44PM +0530, Anand Moon wrote: > > On Mon, 2 Sept 2024 at 00:03, Anand Moon <linux.amoon@gmail.com> wrote: > > > > > > Refactor the clock handling in the Rockchip PCIe driver, > > > introducing a more robust and efficient method for enabling and > > > disabling clocks using clk_bulk*() API. Using the clk_bulk APIs, > > > the clock handling for the core clocks becomes much simpler. > > > > > > Signed-off-by: Anand Moon <linux.amoon@gmail.com> > > > > Do you have any review comments on this series? > > Looks like nice work, thanks. Minor tips below. We'll start applying > PCI patches to v6.13-rc1 after it is tagged. It looks like these will > apply cleanly, so no rebasing needed. > > - It would be helpful if you can add a cover letter (0/n), which is > a good place for the overall diffstat and series-level changelog. > > - This v5 series adds drivers/phy patches, which are also related to > rockchip, but will be handled by a different maintainer, so best > to send them as separate series (and of course send the phy > patches to the right maintainer, linux-phy, etc). > > - "b4 am -o/tmp/ 20240901183221.240361-2-linux.amoon@gmail.com" > complains about something, I dunno how to fix: > > Checking attestation on all messages, may take a moment... > --- > ✗ [PATCH v5 1/6] PCI: rockchip: Simplify clock handling by using clk_bulk*() function > ✗ [PATCH v5 2/6] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function > ✗ [PATCH v5 3/6] PCI: rockchip: Refactor rockchip_pcie_disable_clocks function signature > ✗ [PATCH v5 4/6] phy: rockchip-pcie: Simplify error handling with dev_err_probe() > ✗ [PATCH v5 5/6] phy: rockchip-pcie: Change to use devm_clk_get_enabled() helper > ✗ [PATCH v5 6/6] phy: rockchip-pcie: Use regmap_read_poll_timeout for PCIe reference clk PLL status > --- > ✗ BADSIG: DKIM/gmail.com > > - In 3/6 and 6/6 commit logs, add parens after function names as > you did elsewhere. > > - Super nit: In 5/6, s/Change to use/Use/. Every patch is a change, > so "Change to" doesn't add any information. > Ok, I will try to fix and improve on your suggestion in the next version. > Bjorn Thanks -Anand
diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c index c07d7129f1c7..2777ef0cb599 100644 --- a/drivers/pci/controller/pcie-rockchip.c +++ b/drivers/pci/controller/pcie-rockchip.c @@ -127,29 +127,9 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) "failed to get ep GPIO\n"); } - rockchip->aclk_pcie = devm_clk_get(dev, "aclk"); - if (IS_ERR(rockchip->aclk_pcie)) { - dev_err(dev, "aclk clock not found\n"); - return PTR_ERR(rockchip->aclk_pcie); - } - - rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf"); - if (IS_ERR(rockchip->aclk_perf_pcie)) { - dev_err(dev, "aclk_perf clock not found\n"); - return PTR_ERR(rockchip->aclk_perf_pcie); - } - - rockchip->hclk_pcie = devm_clk_get(dev, "hclk"); - if (IS_ERR(rockchip->hclk_pcie)) { - dev_err(dev, "hclk clock not found\n"); - return PTR_ERR(rockchip->hclk_pcie); - } - - rockchip->clk_pcie_pm = devm_clk_get(dev, "pm"); - if (IS_ERR(rockchip->clk_pcie_pm)) { - dev_err(dev, "pm clock not found\n"); - return PTR_ERR(rockchip->clk_pcie_pm); - } + rockchip->num_clks = devm_clk_bulk_get_all(dev, &rockchip->clks); + if (rockchip->num_clks < 0) + return dev_err_probe(dev, err, "failed to get clocks\n"); return 0; } @@ -372,39 +352,11 @@ int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip) struct device *dev = rockchip->dev; int err; - err = clk_prepare_enable(rockchip->aclk_pcie); - if (err) { - dev_err(dev, "unable to enable aclk_pcie clock\n"); - return err; - } - - err = clk_prepare_enable(rockchip->aclk_perf_pcie); - if (err) { - dev_err(dev, "unable to enable aclk_perf_pcie clock\n"); - goto err_aclk_perf_pcie; - } - - err = clk_prepare_enable(rockchip->hclk_pcie); - if (err) { - dev_err(dev, "unable to enable hclk_pcie clock\n"); - goto err_hclk_pcie; - } - - err = clk_prepare_enable(rockchip->clk_pcie_pm); - if (err) { - dev_err(dev, "unable to enable clk_pcie_pm clock\n"); - goto err_clk_pcie_pm; - } + err = clk_bulk_prepare_enable(rockchip->num_clks, rockchip->clks); + if (err) + return dev_err_probe(dev, err, "failed to enable clocks\n"); return 0; - -err_clk_pcie_pm: - clk_disable_unprepare(rockchip->hclk_pcie); -err_hclk_pcie: - clk_disable_unprepare(rockchip->aclk_perf_pcie); -err_aclk_perf_pcie: - clk_disable_unprepare(rockchip->aclk_pcie); - return err; } EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks); @@ -412,10 +364,7 @@ void rockchip_pcie_disable_clocks(void *data) { struct rockchip_pcie *rockchip = data; - clk_disable_unprepare(rockchip->clk_pcie_pm); - clk_disable_unprepare(rockchip->hclk_pcie); - clk_disable_unprepare(rockchip->aclk_perf_pcie); - clk_disable_unprepare(rockchip->aclk_pcie); + clk_bulk_disable_unprepare(rockchip->num_clks, rockchip->clks); } EXPORT_SYMBOL_GPL(rockchip_pcie_disable_clocks); diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 6111de35f84c..bebab80c9553 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -11,6 +11,7 @@ #ifndef _PCIE_ROCKCHIP_H #define _PCIE_ROCKCHIP_H +#include <linux/clk.h> #include <linux/kernel.h> #include <linux/pci.h> #include <linux/pci-ecam.h> @@ -299,10 +300,8 @@ struct rockchip_pcie { struct reset_control *pm_rst; struct reset_control *aclk_rst; struct reset_control *pclk_rst; - struct clk *aclk_pcie; - struct clk *aclk_perf_pcie; - struct clk *hclk_pcie; - struct clk *clk_pcie_pm; + struct clk_bulk_data *clks; + int num_clks; struct regulator *vpcie12v; /* 12V power supply */ struct regulator *vpcie3v3; /* 3.3V power supply */ struct regulator *vpcie1v8; /* 1.8V power supply */
Refactor the clock handling in the Rockchip PCIe driver, introducing a more robust and efficient method for enabling and disabling clocks using clk_bulk*() API. Using the clk_bulk APIs, the clock handling for the core clocks becomes much simpler. Signed-off-by: Anand Moon <linux.amoon@gmail.com> --- v5: switch to use use devm_clk_bulk_get_all()? gets rid of hardcoding the clock names in driver. v4: use dev_err_probe for error patch. v3: Fix typo in commit message, dropped reported by. v2: Fix compilation error reported by Intel test robot. --- --- drivers/pci/controller/pcie-rockchip.c | 65 +++----------------------- drivers/pci/controller/pcie-rockchip.h | 7 ++- 2 files changed, 10 insertions(+), 62 deletions(-)